Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs (Single In-line Memory Modules) that differ in size and speed of operation. The memory controller is operable, in response to an access request for a given SIMM, to read from a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS (Row Address Strobe) to CAS (Column Address Strobe) time, and CAS pulse width, depending on the SIMM being accessed.