Abstract: A plurality of integrated circuits that are used in an electronic circuit have functional interconnections and dedicated test connections. The integrated circuits receive and transmit synchronization information, such as clock signals from one integrated circuit to another successively through the chain. This permits a high-test speed. Preferably the synchronization information is serialized with test data, test results and/or commands. Preferably, the bit rate between successive integrated circuits in the chain is programmable by means of commands transmitted through the chain. Thus, different bit rates may be at different locations along the chain to reduce the delay occurred by the synchronization signals along the chain.

Abstract: An integrated circuit device has boundary scan structure coupled between a test input (TDI) and the test output (TDO). The test register structure is used to shift information from the test input to a test output. Test data is transported from the input to the output by shifting. The test shift register structure contains a data shift part (106) coupled to connections (12) for a functional circuit under test. In parallel with the data shift part is an instruction shift structure (102, 104). By means of test control signals it is controlled whether instruction information travels from the test input to the test output through the instruction shift part or whether data travels from the test input to the test output through the data shift the instruction shift part controls operation of the device in a test mode. A sensor (14) is provided for sensing a physical operating parameter of the device.