Patents by Inventor Rodney A. Browen

Rodney A. Browen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6467051
    Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: October 15, 2002
    Assignee: Agilent Technologies, Inc.
    Inventors: Rodney A. Browen, Cherif Ahrikencheikh, William P. Darbie, John E. McDermid, Kay C. Lannen
  • Patent number: 6334100
    Abstract: A method for evaluating and correcting a model of an electronic circuit. A list is created which comprises the minimum number of components that must be specified by the operator in order to be able to compute values for the remaining circuit components. Correction of circuit models can be performed even in cases of limited accessibility to the circuit's nodes.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: December 25, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Cherif Ahrikencheikh, Rodney A. Browen, William P. Darbie, Kay C. Lannen, John E. McDermid, Jamie P. Romero
  • Patent number: 6327545
    Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: December 4, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Rodney A. Browen, Cherif Ahrikencheikh, William P. Darbie, John E. McDermid
  • Patent number: 6266787
    Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: July 24, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: John E. McDermid, Cherif Ahrikencheikh, Rodney A. Browen, William P. Darbie, Kay C. Lannen
  • Patent number: 6263476
    Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: July 17, 2001
    Assignee: Agilent Technologies
    Inventors: Rodney A. Browen, Cherif Ahrikencheikh, William P. Darbie, John E. McDermid, Kay C. Lannen
  • Patent number: 6237118
    Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: May 22, 2001
    Assignee: Agilent Technologies
    Inventors: Cherif Ahrikencheikh, Rodney A. Browen, William P. Darbie, John E. McDermid
  • Patent number: 6233706
    Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: May 15, 2001
    Assignee: Agilent Technologies
    Inventors: Cherif Ahrikencheikh, Rodney A. Browen, William P. Darbie, John E. McDermid, Kay C . Lannen
  • Patent number: 4652814
    Abstract: A circuit tester and test technique are presented that compresses the amount of data stored in local test data RAMs for the implementation of a circuit test, thereby reducing the amount of data that must be downloaded to the local test data RAMs, thereby improving test throughput. Derivative data vectors are utilized in addition to raw data vectors as part of the data compression technique. Further compression results from storing only unique data vectors in the local test data RAMs and utilizing a sequencer to control the order in which the unique data vectors are utilized. The sequencer includes test program logic and logic capable of implementing on test pins indirect counters.
    Type: Grant
    Filed: June 13, 1983
    Date of Patent: March 24, 1987
    Assignee: Hewlett-Packard Company
    Inventors: William A. Groves, Matthew L. Snook, Rodney Browen
  • Patent number: 4642561
    Abstract: A circuit tester and test technique are presented that compresses the amount of data stored in local test data RAMs for the implementation of a circuit test, thereby reducing the amount of data that must be downloaded to the local test data RAMs, thereby improving test throughput. Derivative data vectors are utilized in addition to raw data vectors as part of the data compression technique. Further compression results from storing only unique data vectors in the local test data RAMs and utilizing a sequencer to control the order in which the unique data vectors are utilized. The sequencer includes test program logic and logic capable of implementing on test pins indirect counters.
    Type: Grant
    Filed: January 3, 1984
    Date of Patent: February 10, 1987
    Assignee: Hewlett-Packard Company
    Inventors: William A. Groves, Matthew L. Snook, Rodney Browen
  • Patent number: 4598245
    Abstract: A circuit tester and test technique are presented that compresses the amount of data stored in local test data RAMs for the implementation of a circuit test, thereby reducing the amount of data that must be downloaded to the local test data RAMs, thereby improving test throughput. Derivative data vectors are utilized in addition to raw data vectors as part of the data compression technique. Further compression results from storing only unique data vectors in the local test data RAMs and utilizing a sequencer to control the order in which the unique data vectors are utilized. The sequencer includes test program logic and logic capable of implementing on test pins indirect counters.
    Type: Grant
    Filed: January 3, 1984
    Date of Patent: July 1, 1986
    Assignee: Hewlett-Packard Company
    Inventors: William A. Groves, Matthew L. Snook, Rodney Browen