Abstract: An article for securing a mouth piece, comprising a first sheet of plastic or textile material; and a second sheet positioned flush against the first sheet and joined along an outer margin to form a pouch configured to be coupled to clothing or sporting equipment worn or carried by a person during physical activity, and wherein at least one of the first sheet and the second sheet is elastically deformable to expand when all or a portion of the mouth piece is introduced into an interior portion of the pouch through the opening, and to compress against the mouth piece or portion thereof situated within the interior portion of the pouch to secure the mouth piece to the article. Another article for securing a mouth piece, comprising a sheet of plastic or textile material joined to the surface of clothing or sporting equipment to form a pocket.

Abstract: Automation system based on communication network, installed to provides facilities for on-site personnel to monitor/control/configure system and connect equipment required to test system. Can automate specific procedures for activities to eliminate human error. Provides necessary commands to the system, other devices and individual functions which enable/disable operation, change operating configuration or send/retrieve certain information. Independent of other devices which provide real time operation of the system to maintain safe and reliable operation of system whilst changes are being made to system regardless of operating condition of other devices. As an independent device to the system, can be standardized at a particular installation and across multiple installations to reduce personnel training and reduce possibilities of human error due to variability of features provided in other devices.

Abstract: A transceiver providing Fiber Channel data transfer speeds may be implemented in a lower performance process technology as a single unit, thereby reducing cost. A serializer and deserializer each having multiple lower frequency clocks are provided to obtain the equivalent of a high speed clock capable of use in Fiber Channel systems. Lower speed parallel data is converted to higher speed serial data, and vice versa. A digital frequency counter along with a phase detection circuit provides synchronization. Comma detection is provided for data word alignment.

Abstract: A linear voltage-controlled capacitance circuit is provided that includes a plurality of differentially coupled metal-oxide-semiconductor (MOS) varactor pairs. Each MOS varactor pair is operable to receive a same tuning voltage and to receive a bias voltage unique to the MOS varactor pair. The capacitance circuit is operable to generate a positive tank node signal and a negative tank node signal based on the tuning voltage and the bias voltages.

Abstract: A charge pump comprises a first current mirror that injects a first charging current onto a loop filter and a second charging current onto an integrator capacitor. The first and second charging currents are controlled by a first common control signal. The first charging current mirrors the second charging current. A second current mirror drains a first discharging current from the loop filter and a second discharging current from the integrator capacitor. The first and second discharging is currents are controlled by a second common control signal. The first discharging current mirrors the second discharging current. A sampling circuit couples the second charging and discharging currents to the integrator capacitor, which charges or discharges with a difference current between the second charging and discharging currents. A control circuit detects a voltage difference between the loop filter and integrator capacitor and adjusts the first common control signal to minimize the voltage difference.

Abstract: A system and method for providing synchronous clocking allows for precise control of the phase relationship of the clocking signals to thereby provide accurate duty cycles for proper system operation. A digital logic circuit, such as a D-type flip-flop, is provided with a phase signal and clock signal having a frequency relationship. The output of the digital logic circuit is a function of the phase signal and clock signal. The synchronous output may be provided to multiple locations within a system to allow for a synchronous local clock in each of the locations.

Abstract: A charge pump comprises a first current mirror that injects a first charging current onto a loop filter and a second charging current onto an integrator capacitor. The first and second charging currents are controlled by a first common control signal. The first charging current mirrors the second charging current. A second current mirror drains a first discharging current from the loop filter and a second discharging current from the integrator capacitor. The first and second discharging currents are controlled by a second common control signal. The first discharging current mirrors the second discharging current. A sampling circuit couples the second charging and discharging currents to the integrator capacitor, which charges or discharges with a difference current between the second charging and discharging currents. A control circuit detects a voltage difference between the loop filter and integrator capacitor and adjusts the first common control signal to minimize the voltage difference.

Abstract: A system and method for providing synchronous clocking allows for precise control of the phase relationship of the clocking signals to thereby provide accurate duty cycles for proper system operation. A digital logic circuit, such as a D-type flip-flop, is provided with a phase signal and clock signal having a frequency relationship. The output of the digital logic circuit is a function of the phase signal and clock signal. The synchronous output may be provided to multiple locations within a system to allow for a synchronous local clock in each of the locations.

Abstract: A charge pump for injecting a charging current onto a loop filter when a pump control signal is enabled. The charge pump comprises: i) MOS output transistors for injecting or removing the charge onto the loop filter; ii) pre-charge capacitors for storing pre-charge voltages at least equal to the desired gate-to-source voltages of the output transistors; and iii) switching circuitry for coupling the pre-charge capacitors to the gates of the output transistors when the Pump Up and/or Pump Down signals are enabled. The appropriate pre-charge voltage turns on the appropriate output transistor and the charging and/or discharging current is adjusted to a final level determined by the desired gate-to-source voltages and monitoring circuits.

Abstract: A transceiver providing Fiber Channel data transfer speeds may be implemented in a lower performance process technology as a single unit, thereby reducing cost. A serializer and deserializer each having multiple lower frequency clocks are provided to obtain the equivalent of a high speed clock capable of use in Fiber Channel systems. Lower speed parallel data is converted to higher speed serial data, and vice versa. A digital frequency counter along with a phase detection circuit provides synchronization. Comma detection is provided for data word alignment.

Abstract: A transceiver (14) for recovering two different types of manchester coded, optical data signals from a photodiode is disclosed. The transceiver (14) includes a preamplifier (28) that receives and differentially amplifies the optical signal to reject power supply noise. The output of the preamplifier (28) is applied to an AC coupler (30) that extracts DC signal components using a switching circuit to produce a purely differential signal. A post amplifier/quantizer (34) receives the purely differential signal from the AC coupler (30) and generates a quantized signal therefrom. The quantized signal is applied to a data filter, clock recovery and control logic system 36 (36) that recovers a clock signal from the data signal that is synchronized by every data edge of the quantized signal.