Abstract: A litter lift system includes a winch and a lifting strap. The winch includes a rotatable spool. The lifting strap has one end coupled to the rotatable spool and is movable due to rotation of the rotatable spool. The lifting strap has a first lifting segment and a second lifting segment positioned away from the end of the lifting strap coupled to the rotatable spool. The first lifting segment and the second lifting segment are each forked to interface with a frame of a litter at first lifting segment and second lifting segment distal ends, wherein a coupling is attached to the first lifting segment. Rotation of the rotatable spool in a first direction raises the first lifting segment and the second lifting segment. Rotation of the rotatable spool in a second direction different from the first direction lowers the first lifting segment and the second lifting segment.

Abstract: A digital video interface receiver adjusts a transfer function of a phase-locked loop circuit having a programmable charge pump, a programmable phase-locked loop filter, or a programmable gain voltage controlled oscillator. The digital video interface receiver monitors and detects errors in a data stream associated with the phase-locked loop circuit. Moreover, the digital video interface receiver changes the transfer function of the phase-locked loop circuit, in response to the detected errors, by changing parameters associated with the programmable charge pump, the programmable phase-locked loop filter, or the programmable gain voltage controlled oscillator of the phase-locked loop circuit so as to change the transfer function of the phase-locked loop circuit.

Abstract: A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer selects a channel for sampling, and a capacitive coupler capacitively couples the multiplexer to a sampling circuit. The sampling circuit produces sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data. A test circuit compares the sampled data with the data produced by the high-definition multimedia interface encoder.

Abstract: A digital video interface receiver adjusts a transfer function of a phase-locked loop circuit having a programmable charge pump, a programmable phase-locked loop filter, or a programmable gain voltage controlled oscillator. The digital video interface receiver monitors and detects errors in a data stream associated with the phase-locked loop circuit. Moreover, the digital video interface receiver changes the transfer function of the phase-locked loop circuit, in response to the detected errors, by changing parameters associated with the programmable charge pump, the programmable phase-locked loop filter, or the programmable gain voltage controlled oscillator of the phase-locked loop circuit so as to change the transfer function of the phase-locked loop circuit.

Abstract: A digital video interface receiver adjusts a transfer function of a phase-locked loop circuit having a programmable charge pump, a programmable phase-locked loop filter, or a programmable gain voltage controlled oscillator. The digital video interface receiver monitors and detects errors in a data stream associated with the phase-locked loop circuit. Moreover, the digital video interface receiver changes the transfer function of the phase-locked loop circuit, in response to the detected errors, by changing parameters associated with the programmable charge pump, the programmable phase-locked loop filter, or the programmable gain voltage controlled oscillator of the phase-locked loop circuit so as to change the transfer function of the phase-locked loop circuit.

Abstract: A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer selects a channel for sampling, and a capacitive coupler capacitively couples the multiplexer to a sampling circuit. The sampling circuit produces sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data. A test circuit compares the sampled data with the data produced by the high-definition multimedia interface encoder.

Abstract: A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer selects a channel for sampling, and a capacitive coupler capacitively couples the multiplexer to a sampling circuit. The sampling circuit produces sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data. A test circuit compares the sampled data with the data produced by the high-definition multimedia interface encoder.

Abstract: A system and method transmits graphic data received at varying frequencies at a fixed data rate. The frequency dependent data and associated data clock signal are received and the frequency dependent data is converted to frequency independent data. A ratio of a number of data clock cycles to a number of reference clock cycles is determined and transmitted. The frequency independent data and header data are transmitted, at a fixed rate, to a receiver, the fixed rate being a frequency greater than the frequency of the associated data clock signal. The received the frequency independent data is converted to frequency dependent data based upon the received determined ratio. The communication channel may include an optical fiber and a tension member wherein control data is transmitted along the tension member and graphic data is transmitted along the optical fiber.

Abstract: A system and method transmits data received at varying frequencies at a fixed data rate. The frequency dependent data and associated data clock signal are received and the frequency dependent data is converted to frequency independent data. A ratio of a number of data clock cycles to a number of reference clock cycles is determined and transmitted. The frequency independent data and header data are transmitted, at a fixed rate, to a receiver, the fixed rate being a frequency greater than the frequency of the associated data clock signal. The received the frequency independent data is converted to frequency dependent data based upon the received determined ratio. The communication channel may include an optical fiber and a tension member wherein control data is transmitted along the tension member and graphic data is transmitted along the optical fiber.

Abstract: This invention relates to an automated device for loading a centrifuge where tubes are presented to the centrifuge via an automated routing system.

Abstract: This invention relates to an automated device for loading a centrifuge where tubes are presented to the centrifuge via an automated routing system.

Abstract: A system and methods for auctioning consumer demand to suppliers comprising: a request adapter for receiving a first data set in a first protocol, converting the first data set to a second data set in a second intermediate protocol and then, converting the second data set to a third data set in a third protocol; a request preprocessor for receiving the third data set from the request adapter and filtering the third data set; a virtual group processor for receiving the third data set, which has been filtered by the request preprocessor and not rejected, and creating at least one group, including the third data set and other data sets in the third protocol; and a dynamic packaging orchestrator and continuous shopping engine for managing the at least one group, shopping for bids on at least one product represented in the at least one group, and booking the at least one product based on the received bids.

Abstract: An auxiliary line driver (514) able to sense data driven on a signal path (502) by a primary line driver (512), and then drive the data on the signal path (502). The auxiliary driver (514) allows a small primary line driver (512) to drive a large load, or a large number of loads (504, 506) without consuming a large area in the region where the primary line driver (512) is fabricated. The auxiliary line driver is particularly useful for driving the memory array of a micromirror device, especially during a block clear operation in which a large number of memory cells (506) are written to simultaneously. When the auxiliary line driver (514) receives an enable signal (518), the auxiliary line driver drives the last input provided to the input of the auxiliary line driver (514).

Abstract: An improved memory cell (300) for use in applications, such as micromirror arrays, in which little space is available and a slow read-back cycle is tolerated. The memory (300) comprises a first input/output node (314) connected to the input of a first inverter and to the output of a second inverter. The first inverter is comprised of two transistors (304, 306) and drives a signal to a second input/output node (316). The input of the second inverter is connected to the second input/output node (316). When used to drive a typical micromirror cell, the address electrode of the micromirror cell are electrically connected to the first input/output node (314) and the second input/output node (316).

Abstract: A spatial light modulator (70) comprised of an array of micromirrors (72) each having support post (74). The support post (74) defines support post edges (76) in the upper surface of the mirrors (72). These support post edges (76) are all oriented at 45 degree angles with respect to an incident beam of light from a light source (80) to minimize diffraction of light from the edges (76) into the darkfield optics when the mirrors are oriented in the off-state. The present invention achieves an increased contrast ratio of about 20% over conventional designs.

Abstract: A micromirror array fabricated on a semiconductor substrate 708. The micromirrors in the micromirror array logically divided into an interior active region 704 which selectively modulates light striking the mirrors in the interior active region 704, and an exterior border region 702 for producing a dark border around the image produced by the interior active region 704. A gap between each mirror allows adjacent mirrors to rotate. The gap 712 between mirrors in the interior active region 704 of the array is larger than the gap 710 between at least some of the mirrors in the exterior border region 702. The smaller gap 710 in the exterior region 702 is enabled by restricting mirrors in the exterior region 702 to a single direction of rotation.

Abstract: A spatial light modulator (70) comprised of an array of micromirrors (72) each having support post (74). The support post (74) defines support post edges (76) in the upper surface of the mirrors (72). These support post edges (76) are all oriented at 45 degree angles with respect to an incident beam of light from a light source (80) to minimize diffraction of light from the edges (76) into the darkfield optics when the mirrors are oriented in the off-state. The present invention achieves an increased contrast ratio of about 20% over conventional designs.

Abstract: A method of providing control signals for resetting mirror elements (10,20) of a digital micro-mirror device (DMD) having reset groups (FIG. 4), or for resetting moveable elements of other micro-mechanical devices that operate with similar principles. A bias voltage is applied to the mirrors and their landing sites, and an address voltage is applied under the mirrors. (FIG. 3). The address voltage is held at an intermediate level except during a reset period. During this reset period, the address voltage is increased. Also, during reset, the bias applied to mirrors to be reset is pulsed and offset, and the bias applied to mirrors not to be reset is increased. (FIGS. 5 and 6).

Abstract: A method of implementing pulse-width modulated image display systems (10, 20) with a spatial light modulator (SLM) (15) configured for split-reset addressing. Display frame periods are divided into time slices. Each frame of data is divided into bit-planes, each bit-plane having one bit of data for each pixel element and representing a bit weight of the intensity value to be displayed by that pixel element. Each bit-plane has a display time corresponding to a number of time slices, with bit-planes of higher bit weights being displayed for more time slices. The bit-planes are further formatted into reset groups, each reset group corresponding to a reset group of the SLM (15). The display times for reset groups of more significant bits are segmented so that the data can be displayed in segments rather than for a continuous time. During loading, segments of corresponding bit-planes are temporally aligned from one reset group to the next.