Abstract: A system and method of controlling the timing of a clock signal delivered to one or more memory modules, such as SDRAM modules, wherein the system clock speed is relatively fast. The system and method uses a buffer that is similar to other buffers in the system to delay the output of the clock signal in order to provide accurate tracking over differences attributable to process, voltage and temperature. In order to incorporate similar buffer components for the control lines and the clock signal, delay elements are inserted in the timing structure to accurately delay the output timing of the data and control lines as compared to the clock signal. These delay elements, therefore, provide the setup and hold characteristics with a significant amount of accuracy.

Abstract: Systems and methods of controlling the timing of a clock signal used to latch information from one or more memory modules, such as SDRAM modules. The invention relates to generating a latch or read clock signal that relates to the actual SDRAM control clock signal. The generated clock signal accounts for variances due to PVT and PCB trace lengths. In one embodiment, the generated clock signal is fed back from the SDRAM module. That is, the SDRAM control clock signal is conducted serially to the one or more SDRAM modules and then back to the controller. As such, the read clock signal is essentially the same as the SDRAM clock signal. However, the read clock signal is delayed before its return to the controller due to PVT and trace length issues. Importantly however, these delays are similar to the delays associated with the read line information, such that the controller has a significantly precise understanding of when the information on the read lines is available for latching into its buffers.