Patents by Inventor Rodney Gamache

Rodney Gamache has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5630166
    Abstract: A plurality of processors each includes a central processor unit for processing programs at predetermined synchronization priority levels and a cache memory. A memory shared by all of the processors includes an synchronization level table which identifies a processor operating at each synchronization priority level. A common bus interconnects the processors and the memory. When a processor is to execute a program, it adjusts its synchronization priority level to a predetermined synchronization priority level by accessing the synchronization level table over the common bus to determine whether the level is accessible and, if so, places an entry in the table to indicate that the synchronization priority level is occupied. If the synchronization priority level is not accessible, the processor continually monitors the entry in the table over the common bus to determine when it is accessible by monitoring its cache, which contains a copy of the table entry associated with the synchronization priority level.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: May 13, 1997
    Assignee: Digital Equipment Corporation
    Inventors: Rodney Gamache, Stuart Farnham, Michael Harvey, William A. Laing, Kathleen Morse, Michael Uhler
  • Patent number: 5313577
    Abstract: A computer graphics processor capable of reading from, and writing to, virtual memory. The invention provides a graphics processing unit which includes, among other things, an graphic processor in the form of an address generator which retrieves data from memory locations, and writes data to memory locations. The address generator retrieves data from memory locations memory access request directly to a memory control unit, which retrieves the contents of the memory location. Prior to issuing the request, the address generator sends the address to a virtual translation unit, which translates the virtual address to a physical address. The virtual translation/FIFO control unit also contains three translation buffers, in which are stored the most recently accessed virtual addresses, which, in many situations, enables the virtual translation/FIFO control unit to translate the virtual address using less memory accesses.
    Type: Grant
    Filed: August 21, 1991
    Date of Patent: May 17, 1994
    Assignee: Digital Equipment Corporation
    Inventors: Kim Meinerth, Colyn Case, Chris Franklin, Blaise Fanning, Rodney Gamache