Abstract: A computer system includes a computer and a plug-in card having a remote data link. The plug-in card draws power from the power sour the computer. A status monitor shows the operability of the remote data link, specifically whether it is operable for data communications to or from the computer, and its connection to the plug-in card. Power to the plug-in card is controlled responsive to the status monitor, so that power to the card is enabled only when the external data link and its connector are operable.

Abstract: A controller commands the memory refreshment of a pseudo-static random access memory (PSRAM) accessible from a remote host processor. The controller includes a detector for the end of a memory access cycle by the host processor. A tapped delay line is activated by the detector at the end of the memory access cycle of the PSRAM. The tapped delay line produces a series of delay line output signals at a series of preselected times after activation. An automatic refresh of the PSRAM is initiated upon receipt of a first tapped delay line output signal. The automatic refresh is discontinued upon receipt of a second tapped delay line output signal that follows the first tapped delay line output signal by a sufficient time to permit performance of an automatic refresh. Further refresh cycles can be initiated if the host does not seek memory access, and the further refresh cycles can begin immediately or be delayed by some selected amount of time.

Abstract: An apparatus used to interface a peripheral device to a computer has an adapter card that plugs into the computer and a smart cable that plugs into the adapter card at one end and the peripheral device at the other. The adapter card includes a reconfigurable interface circuit that is in communication with the computer when the adapter card is connected to the computer. The smart cable includes a first memory containing configuration information for the reconfigurable interface circuit, and a second memory containing adapter card information structure information for the reconfigurable interface circuit. The two memories are accessible by the reconfigurable interface circuit when the smart cable is connected to the adapter card. The smart cable further includes a peripheral device interface circuit communicating with the reconfigurable interface circuit and with the peripheral device when the smart cable is connected to the adapter card and the peripheral device is connected to the smart cable.