Abstract: A novel, nonvolatile, floating gate memory structure, and a method for its fabrication, is described wherein the floating gate is substantially shielded from the substrate by the program or control gate. The program or control gate is provided with an aperture located over an auxiliary channel region. A portion of the floating gate is formed to extend through the aperture to allow charge to be played on the floating gate.

Abstract: A novel, nonvolatile floating gate memory structure is described wherein the floating gate is substantially shielded from the substrate by the control gate. The control gate is provided with a pair of apertures, through which portions of the floating gate extends. One aperture serves as means for "writing" and "erasing" while the other aperture serves as means for "reading".

Abstract: By dividing the split gate electrode into four sections, in which two non-adjacent sections are solely clock sections and the other two sections are "plus" and "minus" sections, respectively, and in which the sum of the lengths of the first two sections, in serial order, is substantially equal to the sum of the last two sections, in serial order, only a single mask must be changed, in the fabrication of transversal filters that exhibit a small common mode, in order to change the particular filter characteristic of a fabricated filter.

Abstract: Digital control means responsive to an applied digital signal controls which row or rows of an N row-Q column CCD imager are effective in transferring charge and which are not. Such digital control is suitable for use in providing variable gain for a time-delay integration (TDI) charge-transfer imager in accordance with the average brightness level of the light incident on the imager.

Abstract: A method of manufacturing a closed gate MOS transistor having a self-aligned drain contact is presented which insures that the drain contact will have the minimum required geometry. The method employs a self-aligned procedure which insures that the drain contact will have the minimum dimensions to insure a high speed device.

Abstract: A method of manufacturing a closed gate MOS transistor having a self-aligned drain contact is presented which insures that the drain contact will have the minimum required geometry. The method employs a self-aligned procedure which insures that the drain contact will be the minimum dimensions to insure a high speed device. Also, the completed device includes a dual layer passivation overcoat which insures a hermetically sealed device.

Abstract: The output register of a CCD imager system is loaded at high speed by, for each row of charges, first translating the m charges in each group of m adjacent ones of the n columns of the imager into m serially occurring charges and temporarily storing each group of m serially occurring charges in a separate CCD register. The time available for the translation and temporary storage is equal to the time required serially to read out the output register. The n/m temporarily stored groups of charges are then concurrently serially shifted from the n/m registers in which they are stored to the output register which comprises m parallel registers, each with n/m stages. This shifting for loading the register can be performed at very high speed.

Abstract: Charge-coupled device (CCD) including a plurality of parallel CCD channels and common electrodes extending over these channels for controlling the flow of charge in the channels. Potential barrier regions are located beneath certain of the electrodes in certain of the channels, each pair of barrier regions separated by a normal channel region, and voltages are applied to the electrodes at levels such that charge in a channel containing the barrier regions is trapped and temporarily delayed in the normal channel region between the barrier regions relative to the propagation of charge in a channel not containing barrier regions. The structure is useful, for example, in tree networks for parallel-to-serial signal translation and vice versa.