Patents by Inventor Rodney N. Mullendore
Rodney N. Mullendore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11704023Abstract: A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.Type: GrantFiled: March 21, 2022Date of Patent: July 18, 2023Assignee: Western Digital Technologies, Inc.Inventors: Rajesh Koul, Rodney N. Mullendore, James J. Walsh
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Publication number: 20220214816Abstract: A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.Type: ApplicationFiled: March 21, 2022Publication date: July 7, 2022Applicant: Western Digital Technologies, Inc.Inventors: Rajesh KOUL, Rodney N. MULLENDORE, James J. WALSH
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Patent number: 11314418Abstract: A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.Type: GrantFiled: March 23, 2021Date of Patent: April 26, 2022Assignee: Western Digital Technologies, Inc.Inventors: Rajesh Koul, Rodney N. Mullendore, James J. Walsh
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Publication number: 20210208789Abstract: A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.Type: ApplicationFiled: March 23, 2021Publication date: July 8, 2021Inventors: Rajesh KOUL, Rodney N. MULLENDORE, James J. WALSH
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Patent number: 10990293Abstract: A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.Type: GrantFiled: March 17, 2020Date of Patent: April 27, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Rajesh Koul, Rodney N. Mullendore, James J. Walsh
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Publication number: 20200218457Abstract: A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.Type: ApplicationFiled: March 17, 2020Publication date: July 9, 2020Inventors: Rajesh KOUL, Rodney N. MULLENDORE, James J. WALSH
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Patent number: 10642503Abstract: A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.Type: GrantFiled: June 25, 2019Date of Patent: May 5, 2020Assignee: Western Digital Technologies, Inc.Inventors: Rajesh Koul, Rodney N. Mullendore, James J. Walsh
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Publication number: 20190310779Abstract: A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.Type: ApplicationFiled: June 25, 2019Publication date: October 10, 2019Inventors: Rajesh KOUL, Rodney N. MULLENDORE, James J. WALSH
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Patent number: 10372346Abstract: A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.Type: GrantFiled: July 27, 2017Date of Patent: August 6, 2019Assignee: Western Digital Technologies, Inc.Inventors: Rajesh Koul, Rodney N. Mullendore, James J. Walsh
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Patent number: 10254983Abstract: A method of performing an atomic write command in a data storage device comprising a volatile memory and a plurality of non-volatile memory devices configured to store a plurality of physical pages. The method may comprise storing data in a plurality of logical pages (L-Pages), each associated with a logical address. A logical-to-physical address translation map may be maintained in the volatile memory, and may be configured to enable determination of a physical location, within one or more of the physical pages, of the data referenced by each logical address. The data specified by a received atomic write command may be stored one or more L-Pages. Updates to the entry or entries in the translation map associated with the L-Page(s) storing the data specified by the atomic write command may be deferred until all L-Pages storing data specified by the atomic write command have been written in a power-safe manner.Type: GrantFiled: March 14, 2017Date of Patent: April 9, 2019Assignee: Western Digital Technologies, Inc.Inventors: Andrew J. Tomlin, Justin Jones, Rodney N. Mullendore
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Patent number: 10082957Abstract: A storage cartridge may include a storage controller comprising a single PCIe port and a PCIe switch. The PCIe switch may include a first PCIe port communicatively coupled to a first PCIe fabric, a second PCIe port communicatively coupled to a second, different PCIe fabric, and a third PCIe port communicatively coupled to the single PCIe port of the storage controller. The first PCIe port and the second PCIe port may be configured to be selectively communicatively coupled to a non-transparent bridge (NTB) of the PCIe switch.Type: GrantFiled: July 20, 2016Date of Patent: September 25, 2018Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Pinchas Herman, Vijay Karamcheti, Rodney N. Mullendore, William H. Radke
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Patent number: 10061696Abstract: A method for managing garbage collection of memory locations in an DSD having a plurality of dies each having a plurality of memory blocks includes: selecting a physical region of memory to be garbage collected, the selected physical region being a subset of a block management region; and garbage collecting the selected physical region. The garbage collecting includes: determining one or more journals corresponding to the selected physical region, the journal comprising transaction entries indicating what logical data are written to memory locations in the selected physical region; determining whether the memory locations within the physical region contain valid data based on a comparison of information in the journal and a mapping table; and if valid data exists, copying valid data into memory locations in memory regions other than the selected physical region of memory. The selected physical region of memory is erased when the block management region is erased.Type: GrantFiled: May 27, 2016Date of Patent: August 28, 2018Assignee: Western Digital Technologies, Inc.Inventors: Justin Jones, Andrew J. Tomlin, Paul Sweazey, Johnny A. Lam, Rodney N. Mullendore
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Patent number: 10055345Abstract: A solid state drive controller includes a processor configured to couple to a plurality of non-volatile memory devices. The plurality of non-volatile memory devices are configured to store a plurality of system journals and a plurality of physical pages. The solid state drive controller also includes a volatile memory configured to store a logical-to-physical address translation map configured to enable the solid state drive controller to determine a physical location of at least one logical page. The processor is configured to maintain the plurality of system journals in the plurality of non-volatile memory devices, wherein each system journal defines physical-to-logical page correspondences for a predetermined range of the plurality of physical pages, and each system journal comprises an identification number that includes a portion of an address of a first physical page of the predetermined range of the plurality of physical pages.Type: GrantFiled: November 7, 2016Date of Patent: August 21, 2018Assignee: Western Digital Technologies, Inc.Inventors: Andrew J. Tomlin, Rodney N. Mullendore, Justin Jones
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Patent number: 9948322Abstract: A method of merging data frames includes: receiving a first data frame having a plurality of sectors; receiving a second data frame having a plurality of sectors; generating a merged output data frame by merging, using a plurality of data paths including a plurality of multiplexers, sectors of the second data frame with sectors of the first data frame; and performing an error check on at least one check-data frame having sectors corresponding to those in the first data frame or the second data frame, where at least some of the sectors in the check-data frame are transmitted on a subset of the plurality of data paths that transmits sectors of the merged output data frame, and where the error check verifies the merged output data frame.Type: GrantFiled: April 28, 2015Date of Patent: April 17, 2018Assignees: WESTERN DIGITAL TECHNOLOGIES, INC., SKYERA, LLCInventors: Jack W. Flinsbaugh, Rodney N. Mullendore
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Publication number: 20180032267Abstract: A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.Type: ApplicationFiled: July 27, 2017Publication date: February 1, 2018Inventors: Rajesh KOUL, Rodney N. Mullendore, James J. Walsh
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Publication number: 20180024743Abstract: A storage cartridge may include a storage controller comprising a single PCIe port and a PCIe switch. The PCIe switch may include a first PCIe port communicatively coupled to a first PCIe fabric, a second PCIe port communicatively coupled to a second, different PCIe fabric, and a third PCIe port communicatively coupled to the single PCIe port of the storage controller. The first PCIe port and the second PCIe port may be configured to be selectively communicatively coupled to a non-transparent bridge (NTB) of the PCIe switch.Type: ApplicationFiled: July 20, 2016Publication date: January 25, 2018Inventors: Pinchas Herman, Vijay Karamcheti, Rodney N. Mullendore, William H. Radke
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Patent number: 9866484Abstract: Systems, methods and software useful for overcoming network congestion problems including head-of-line blocking issues and other network congestion problems. In certain aspects, flow control mechanisms implemented in a switch device or other network device manage buffer and system level resources using a scheduler to control the amount of data requested from a local SAN fabric. Switches and other network devices configured according to the present invention monitor each individual SCSI task, and are configured to apply flow control measures to each active session when buffering resources become scarce, such as when buffering data for a slower-speed WAN link or TCP/IP based interconnects of any speed.Type: GrantFiled: August 14, 2015Date of Patent: January 9, 2018Assignee: Brocade Communications Systems, Inc.Inventors: Rodney N. Mullendore, Joseph L. White
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Publication number: 20170344287Abstract: A method of performing an atomic write command in a data storage device comprising a volatile memory and a plurality of non-volatile memory devices configured to store a plurality of physical pages. The method may comprise storing data in a plurality of logical pages (L-Pages), each associated with a logical address. A logical-to-physical address translation map may be maintained in the volatile memory, and may be configured to enable determination of a physical location, within one or more of the physical pages, of the data referenced by each logical address. The data specified by a received atomic write command may be stored one or more L-Pages. Updates to the entry or entries in the translation map associated with the L-Page(s) storing the data specified by the atomic write command may be deferred until all L-Pages storing data specified by the atomic write command have been written in a power-safe manner.Type: ApplicationFiled: March 14, 2017Publication date: November 30, 2017Inventors: Andrew J. Tomlin, Justin Jones, Rodney N. Mullendore
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Patent number: 9817577Abstract: A data storage device comprises a non-volatile memory comprising a plurality of blocks, each configured to store a plurality of physical pages at predetermined physical locations. A controller programs and reads data stored in a plurality of logical pages. A volatile memory comprises a logical-to-physical address translation map configured to enabling determination of the physical location, within one or more physical pages, of the data stored in each logical page. A plurality of journals may be stored, each comprising a plurality of entries associating one or more physical pages to each logical page. At startup, the controller may read at least some of the plurality of journals in an order and rebuild the map; indicate a readiness to service data access commands after the map is rebuilt; rebuild a table from the map and, based thereon, select block(s) for garbage collection after having indicated the readiness to process the commands.Type: GrantFiled: September 26, 2016Date of Patent: November 14, 2017Assignees: Western Digital Technologies, Inc., Skyera, LLCInventors: Andrew J. Tomlin, Justin Jones, Rodney N. Mullendore
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Patent number: 9778885Abstract: In various embodiments, a high-density solid-state storage unit includes a plurality of flash cards. Each flash card has a flash controller that incorporates one or more resources for facilitating compression and decompression operations. In one aspect, data reduction and data reconstruction operations can be performed in-line as data is stored to and retrieved from flash memory. In another aspect, data reduction and data reconstruction operations can be performed as a service. Any one of the plurality of flash cards can be used to provide data reduction or data reconstruction services on demand for any type of data, including system data, libraries, and firmware code.Type: GrantFiled: December 17, 2013Date of Patent: October 3, 2017Assignee: Skyera, LLCInventors: Radoslav Danilak, Rodney N. Mullendore