Patents by Inventor Rodney R. Rozman
Rodney R. Rozman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8489780Abstract: Some embodiments of the invention may use a single control line signal as both a wake up signal and as an indicator of a device selection command. In a command-based protocol on a non-volatile memory bus, a host memory controller may assert a signal on a control line to bring all the memory devices on the bus into an operational mode, while concurrently placing a device selection command on the input/output lines. The memory device selected by the selection command may remain operational to perform a sequence of operations as directed by the host controller. The remaining (non-selected) memory devices may return to a sleep mode until a new signal on the control line is received, indicating a new selection command.Type: GrantFiled: December 21, 2006Date of Patent: July 16, 2013Assignee: Intel CorporationInventors: Rajesh Sundaram, Rodney R. Rozman, Sanjay S. Talreja
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Patent number: 8458415Abstract: Some embodiments of the invention pertain to a memory system containing multiple memory devices, in which one or multiple ones of the memory devices may flexibly be selected at one time for a common operation to be performed by all the selected devices concurrently.Type: GrantFiled: July 27, 2011Date of Patent: June 4, 2013Assignee: Intel CorporationInventors: Shekoufeh Qawami, Rodney R. Rozman, Sean S. Eilert
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Publication number: 20120047334Abstract: Some embodiments of the invention pertain to a memory system containing multiple memory devices, in which one or multiple ones of the memory devices may flexibly be selected at one time for a common operation to be performed by all the selected devices concurrently.Type: ApplicationFiled: July 27, 2011Publication date: February 23, 2012Inventors: Shekoufeh Qawami, Rodney R. Rozman, Sean S. Eilert
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Patent number: 8006044Abstract: Some embodiments of the invention pertain to a memory system containing multiple memory devices, in which one or multiple ones of the memory devices may flexibly be selected at one time for a common operation to be performed by all the selected devices concurrently.Type: GrantFiled: December 21, 2006Date of Patent: August 23, 2011Assignee: Intel CorporationInventors: Shekoufeh Qawami, Rodney R. Rozman, Sean S. Eilert
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Patent number: 7802061Abstract: Some embodiments of the invention use a command-based interface to control reads and writes with non-volatile memory devices. This may reduce the number of pins that are needed on each integrated circuit, and therefore reduce the cost and size of those integrated circuits. In some embodiments, an on-die cache buffer may be used to buffer data transfers between a high-speed memory bus and the slower speed non-volatile array.Type: GrantFiled: December 21, 2006Date of Patent: September 21, 2010Assignee: Intel CorporationInventors: Shekoufeh Qawami, Rodney R. Rozman, Sean S. Eilert
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Patent number: 7693244Abstract: A system, apparatus, method and article to encode, clock recover, and sample data bits are described. The apparatus may include a pulsed digital module comprising a first clock input, a first data input, a data output, and a reset input. The first clock input to receive an encoded signal from a single-wire. The encoded signal comprising a serial bit sequence comprising a clock signal embedded encoded data bit. The pulsed digital module to capture an edge of the encoded signal at the first clock input in accordance with a logic level coupled to the first data input. A delay module comprising a delay input is coupled to the data output and a delay output is coupled to the reset input. The delay module to delay the captured edge by a predetermined period and to generate a delay signal from the delay output after the predetermined period. The pulsed digital module is to generate a first clock edge of the sampling clock at the data output after the predetermined period.Type: GrantFiled: March 31, 2006Date of Patent: April 6, 2010Assignee: Intel CorporationInventors: Sunil Gupta, Rodney R. Rozman
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Patent number: 7650459Abstract: Various embodiments of the invention connect multiple non-volatile memory controllers in a daisy chain manner, so the multiple memory devices may be accessed from a common host controller. Data and control signals may be daisy-chained in this way, so that many memory devices may be connected together, while not increasing the loading on individual signals lines. Transfer with the various memory devices may be interleaved, so that the relatively slow times of the memory devices doesn't slow down the overall throughout of the memory stem.Type: GrantFiled: December 21, 2006Date of Patent: January 19, 2010Assignee: Intel CorporationInventors: Sean S. Eilert, Rodney R. Rozman
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Patent number: 7567471Abstract: In various embodiments, a plurality of non-volatile memory devices, such as NAND flash memory device, may be connected to a host controller device in a fanned out configuration that allows each of the plurality of memory devices to perform read and/or write operations simultaneously. Each non-volatile memory device may include high speed input circuitry and high speed output circuitry so that transfers to and from memory are not limited by the speed of the flash memory read/write interface.Type: GrantFiled: December 21, 2006Date of Patent: July 28, 2009Assignee: Intel CorporationInventors: Sean S. Eilert, Rodney R. Rozman, Shekoufeh Qawami, Glenn Hinton
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Publication number: 20080151622Abstract: Some embodiments of the invention use a command-based interface to control reads and writes with non-volatile memory devices. This may reduce the number of pins that are needed on each integrated circuit, and therefore reduce the cost and size of those integrated circuits. In some embodiments, an on-die cache buffer may be used to buffer data transfers between a high-speed memory bus and the slower speed non-volatile array.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Inventors: Shekoufeh Qawami, Rodney R. Rozman, Sean S. Eilert
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Publication number: 20080155287Abstract: Some embodiments of the invention may use a single control line signal as both a wake up signal and as an indicator of a device selection command. In a command-based protocol on a non-volatile memory bus, a host memory controller may assert a signal on a control line to bring all the memory devices on the bus into an operational mode, while concurrently placing a device selection command on the input/output lines. The memory device selected by the selection command may remain operational to perform a sequence of operations as directed by the host controller. The remaining (non-selected) memory devices may return to a sleep mode until a new signal on the control line is received, indicating a new selection command.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Inventors: Rajesh Sundaram, Rodney R. Rozman, Sanjay S Talreja
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Publication number: 20080155207Abstract: Various embodiments of the invention connect multiple non-volatile memory controllers in a daisy chain manner, so the multiple memory devices may be accessed from a common host controller. Data and control signals may be daisy-chained in this way, so that many memory devices may be connected together, while not increasing the loading on individual signals lines. Transfer with the various memory devices may be interleaved, so that the relatively slow times of the memory devices doesn't slow down the overall throughout of the memory stem.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Inventors: Sean S. Eilert, Rodney R. Rozman
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Publication number: 20080151648Abstract: In various embodiments, a plurality of non-volatile memory devices, such as NAND flash memory device, may be connected to a host controller device in a fanned out configuration that allows each of the plurality of memory devices to perform read and/or write operations simultaneously. Each non-volatile memory device may include high speed input circuitry and high speed output circuitry so that transfers to and from memory are not limited by the speed of the flash memory read/write interface.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Inventors: Sean S. Eilert, Rodney R. Rozman, Shekoufeh Qawami, Glenn Hinton
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Publication number: 20080155204Abstract: Some embodiments of the invention pertain to a memory system containing multiple memory devices, in which one or multiple ones of the memory devices may flexibly be selected at one time for a common operation to be performed by all the selected devices concurrently.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Inventors: Shekoufeh Qawami, Rodney R. Rozman, Sean S. Eilert
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Patent number: 7093064Abstract: A status register for a memory device. The status register provides a programming suspend status signal and a protection status signal. The programming suspend status signal indicates whether a programming operation is suspended. If the processor knows that a programming operation to a specific memory location is suspended, then the processor may request that a data modification operation to another memory location be performed while the programming operation is suspended. The protection status signal indicates whether an attempted data modification operation failed due to a protected memory block versus another type of device failure. Protecting or locking a memory block prevents the modification of data stored in a particular memory block.Type: GrantFiled: August 25, 2004Date of Patent: August 15, 2006Assignee: Intel CorporationInventors: Vishram P. Dalvi, Rodney R. Rozman
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Patent number: 6671785Abstract: A status register for a memory device. The status register provides a programming suspend status signal and a protection status signal. The programming suspend status signal indicates whether a programming operation is suspended. If the processor knows that a programming operation to a specific memory location is suspended, then the processor may request that a data modification operation to another memory location be performed while the programming operation is suspended. The protection status signal indicates whether an attempted data modification operation failed due to a protected memory block versus another type of device failure. Protecting or locking a memory block prevents the modification of data stored in a particular memory block.Type: GrantFiled: April 21, 2000Date of Patent: December 30, 2003Assignee: Intel CorporationInventors: Vishram P. Dalvi, Rodney R. Rozman
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Patent number: 6597605Abstract: Systems including a bit sequence program controller to program in sequence non-volatile memory cells in an array of programmable non-volatile memory cells. The bit sequence program controller determines the bits that require programming by comparing the bits of the program word with an erased logical state of the array of programmable non-volatile memory cells. The bit sequence program controller further indicates which non-volatile memory cells in a word of non-volatile memory cells in the array of non-volatile memory cells require programming to match the program word. The bit sequence program controller counts the number of the bits that require programming in the program word by counting the number of bits of the program word that are not in an erased logical state to determine when the programming should be completed.Type: GrantFiled: May 3, 2002Date of Patent: July 22, 2003Assignee: Intel CorporationInventors: Jerry A. Kreifels, Rodney R. Rozman
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Publication number: 20020126537Abstract: Systems including a bit sequence program controller to program in sequence non-volatile memory cells in an array of programmable non-volatile memory cells. The bit sequence program controller determines the bits that require programming by comparing the bits of the program word with an erased logical state of the array of programmable non-volatile memory cells. The bit sequence program controller further indicates which nonvolatile memory cells in a word of non-volatile memory cells in the array of non-volatile memory cells require programming to match the program word. The bit sequence program controller counts the number of the bits that require programming in the program word by counting the number of bits of the program word that are not in an erased logical state to determine when the programming should be completed.Type: ApplicationFiled: May 3, 2002Publication date: September 12, 2002Inventors: Jerry A. Kreifels, Rodney R. Rozman
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Publication number: 20020095545Abstract: A status register for a memory device. The status register provides a programming suspend status signal and a protection status signal. The programming suspend status signal indicates whether a programming operation is suspended. If the processor knows that a programming operation to a specific memory location is suspended, then the processor may request that a data modification operation to another memory location be performed while the programming operation is suspended. The protection status signal indicates whether an attempted data modification operation failed due to a protected memory block versus another type of device failure. Protecting or locking a memory block prevents the modification of data stored in a particular memory block.Type: ApplicationFiled: April 21, 2000Publication date: July 18, 2002Inventors: Vishram P . Dalvi, Rodney R. Rozman
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Patent number: 6418059Abstract: A bit sequence program controller to program in sequence non-volatile memory cells in an array of programmable non-volatile memory cells. The bit sequence program controller determines the bits that require programming by comparing the bits of the program word with an erased logical state of the array of programmable non-volatile memory cells. The bit sequence program controller further indicates which non-volatile memory cells in a word of non-volatile memory cells in the array of non-volatile memory cells require programming to match the program word. The bit sequence program controller counts the number of the bits that require programming in the program word by counting the number of bits of the program word that are not in an erased logical state to determine when the programming should be completed.Type: GrantFiled: June 26, 2000Date of Patent: July 9, 2002Assignee: Intel CorporationInventors: Jerry A. Kreifels, Rodney R. Rozman
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Patent number: RE42551Abstract: A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.Type: GrantFiled: March 7, 2002Date of Patent: July 12, 2011Inventors: Vishram Prakash Dalvi, Rodney R. Rozman, Christopher John Haid, Jerry Kreifels, Joseph Tsang, Jeff Evertt, Jahanshir J. Javanifard, Jeffrey J. Peterson