Abstract: A chopper-stabilized circuit (1) includes pre-chopping circuitry (26) for chopping an input signal (Vin) at a first frequency to generate a first signal. Input chopping circuitry (9) chops the first signal at a second frequency substantially greater than the first frequency to produce a second signal. The first frequency is a sub-harmonic of the second frequency. Post-chopping circuitry (30) chops the second chopped signal at the first frequency to produce a third signal that is applied to an input of a signal conditioning circuit (2). The output chopping circuitry (10) chops an output of the signal conditioning circuit at the second frequency to generate a fourth signal. The fourth signal is filtered.

Abstract: A chopper-stabilized circuit (1) includes pre-chopping circuitry (26) for chopping an input signal (Vin) at a first frequency to generate a first signal. Input chopping circuitry (9) chops the first signal at a second frequency substantially greater than the first frequency to produce a second signal. The first frequency is a sub-harmonic of the second frequency. Post-chopping circuitry (30) chops the second chopped signal at the first frequency to produce a third signal that is applied to an input of a signal conditioning circuit (2). The output chopping circuitry (10) chops an output of the signal conditioning circuit at the second frequency to generate a fourth signal. The fourth signal is filtered.

Abstract: An integrated voltage controlled current source device is provided, that extends the high accuracy, low drift output current over a large current range, and provides more headroom and better power efficiency than the standard shunt resistor and INA (instrumentation amplifier) current source arrangement. The device has a control voltage input, a load current output and a current set terminal for a connection of a current set resistor. It contains a selected leg biasing set voltage, corresponding to a control voltage applied to the control voltage input of a regulating driver amplifier providing a regulated voltage to be applied across the current set resistor, thereby causing a reference current to flow through the current set resistor and selected leg(s) of a current mirror. Furthermore, the device contains a dynamically matched current mirror that mirrors the reference current to the load output current. The algorithm for selecting the current mirror legs may be a pseudo-random or a defined pattern.

Abstract: Methods and apparatus to provide increased current to a cascode amplifier to maximize slew rate are disclosed. The amplifier has a first input coupled to an input switch and a load circuit for amplifying an input voltage on the first input. A slewing input voltage to the amplifier is detected. Current is increased to the load circuit to increase the slew rate of an output voltage.

Abstract: An integrated circuit driver structure, comprising an amplifier, a current mirror block and an external current set resistor, is provided that is digitally configurable to operate in a current output mode or in a voltage output mode with its output level controlled by an external voltage. The current mirror block comprises multiple current sources, all having the same gate bias supplied by the output of amplifier. At any time, at least one current source is connected to supply the reference current to resistor, while all other current sources are connected to mirror the reference current to the load current output towards the load. A current gain ratio is based on the number of current sources connected to supply resistor and the number connected to mirror the reference current.

Abstract: Methods and apparatus to provide increased current to a cascode amplifier to maximize slew rate are disclosed. The amplifier has a first input coupled to an input switch and a load circuit for amplifying an input voltage on the first input. A slewing input voltage to the amplifier is detected. Current is increased to the load circuit to increase the slew rate of an output voltage.

Abstract: A chopper-stabilized amplifier receiving an input signal includes a first operational transconductance amplifier having an input chopper and an output chopper for chopping an output signal produced by the first operational transconductance amplifier. A switched capacitor notch filter filters the chopped output signal by operating synchronously with the chopping frequency of output chopper to filter ripple voltages that otherwise would be produced by the output chopper. In one embodiment, a second operational transconductance amplifier amplifies the notch filter output. The input signal is fed forward, summed with the output of the second operational transconductance amplifier, and applied to the input of a fourth operational transconductance amplifier. Ripple noise and offset are substantially reduced.

Abstract: An improved method and circuit for reduced settling time in an amplifier are provided. The amplifier comprises a composite amplifier circuit including a first amplifier configured with a second amplifier comprising an integrator circuit. The reduced settling time is facilitated through implementation of a faster path configured between an inverting input terminal of the second amplifier and an output terminal of the first amplifier for current needed by an integrator resistor due to any signal appearing at said inverting input terminal for said high-speed amplifier. The faster path can be realized through the addition of a compensation capacitor between the output terminal of the composite amplifier circuit and the inverting input terminal of the second amplifier. The compensation capacitor can comprise various values depending on any given number of design criteria.

Abstract: An output stage circuit is configured for enabling an output of an amplifier circuit to be pulled upwards and/or downwards to or beyond an upper power supply or below a lower power supply. The exemplary output stage circuit comprises a pair of output transistors configured to provide an output voltage, and a controlled resistive circuit. The controlled resistive element is configured to enhance the gain of the output stage circuit by modifying the dynamic impedance effect of the upper output transistor during pull-up operation, or the lower output transistor during pull-down operation. During normal operation, the controlled resistive element operates with low resistance, e.g., acts as a “short,” but during the pull-up or pull-down operation the controlled resistive element can be configured to add resistance to modify the dynamic impedance of the upper or lower output transistor.

Abstract: A complementary output stage in integrated circuit includes a P-channel transistor (MP1) the segmented into a first group of sections (MP1-1,2 . . . 12) and an N-channel transistor (MN1) segmented into a second group of sections (MN1-1,2 . . . 12). The sections of the first group are disposed in a plurality of N-type well regions (35), respectively, and the sections of the second group are disposed in a plurality of P-type well regions (36), respectively. The sections of the first group are alternately located with respect to the sections of the second group so as to form an interdigitated output stage area of the integrated circuit including the P-channel transistor (MP1) and the N-channel transistor (MN1) so that the higher amount of heat normally generated in the N-channel transistor is dissipated over the entire interdigitated output stage area and reduces peak temperatures in the N-channel transistor.

Abstract: A method and circuit for providing a faster overload recovery time for an amplifier circuit is provided. An overload recovery circuit is configured to reduce and/or eliminate the slow tail voltage that may be caused by overloading a composite amplifier, and thus provide a faster overload recovery time over a wide range of feedback components for the composite amplifier. The overload recovery circuit comprises a bypass device configured to provide a path for additional current to flow through during overload conditions, thus creating a “clamping” action with the feedback element of the amplifier circuit. As a result, the current flowing through the bypass device of the amplifier circuit will be large enough to hold an inverting node of the composite amplifier at the common mode voltage, thus reducing the overload recovery time.

Abstract: A barrier region provided in the active surface of a wafer-level chip scale package device or chip (WCSP device or chip) to substantially reduce the amount of photon-generated substrate current that reaches active circuitry within the active area of the chip.

Abstract: A method and apparatus for auto-calibrating an electronic device without interrupting normal operation of the device. An electronic device configured as a high voltage difference amplifier is disclosed having a calibration circuit which couples a calibration excitation signal to a common-mode signal path of the difference amplifier. The difference amplifier includes a variable transfer function circuit which may be used to adjust the common-mode rejection of the difference amplifier. The calibration excitation signal may be a random, pseudo-random, out-of-band, or other frequency shaped signal generated in reference to a clock signal. A calibration error signal is detected from an output signal. The variable transfer function circuit can be adjusted in response to the detected error signal to reduce the calibration error signal. As a result, common-mode rejection errors of the difference amplifier may be reduced while the difference amplifier is coupled to an input signal source.

Abstract: A charge pump circuit is configured for charging of parasitic capacitances associated with charge pump capacitors in a manner that minimizes voltage ripple. The charge pump circuit is suitably configured with an independent charging circuit configured for supplying the current needed to charge the parasitic capacitances, rather than utilizing the reservoir capacitor to supply the needed current. The independent charging circuit can be implemented with various configurations of charge pump circuits, such as single phase or dual phase charge pumps, and/or doubler, tripler or inverter configurations. The independent charging circuit includes a parasitic charging capacitor or other voltage source configured with one or more switch devices configured to facilitate charging of the parasitics during any phases of operation of the charge pump circuit.

Abstract: An operational amplifier is configured for low voltage operation and better compliance. An exemplary operational amplifier comprises a folded-cascode amplifier with a class-AB biased output stage configured for low voltage operation. The exemplary output stage includes a class-AB control loop being controlled for the upper output device, and with the complementary, lower output device being driven through an additional gain configuration to allow for the necessary compliance voltage. In addition, the lower output device can be configured to operate with a low gate-source voltage.

Abstract: A circuit is provided that can provide, in a single package, a circuit to monitor a sensing element which uses a variable resistor. The circuit (also known as a signal conditioning circuit) may contain resistor input terminals to which a reference set resistor and a resistive sensor can be attached. A reference voltage signal can be applied to both terminals. There are also a circuit for sensing the resulting current flowing through both the set resistor and the resistive sensor. The difference of the currents flowing through each element can then be monitored as being indicative of the difference in resistance between the set resistor and the resistive sensor. The current difference signal can be used to generate a voltage difference signal indicative of the difference in resistance between the set resistor and the resistive sensor. The signal conditioning circuit may be used to adjust the temperature of various devices.

Abstract: An operational amplifier is configured for low voltage operation and better compliance. An exemplary operational amplifier comprises a folded-cascode amplifier with a class-AB biased output stage configured for low voltage operation. The exemplary output stage includes a class-AB control loop being controlled for the upper output device, and with the complementary, lower output device being driven through an additional gain configuration to allow for the necessary compliance voltage. In addition, the lower output device can be configured to operate with a low gate-source voltage.

Abstract: An output stage compensation circuit and method for a low drop-out regulator configured to facilitate stable operation while providing output voltage and current to downstream circuit devices is provided. An exemplary low drop-out regulator is configured with an output stage compensation circuit including one or more segmented sense devices configured to drive one or more fixed current sources. Each segmented sense device is configured to compensate a suitable range of output current and to multiply the effect of associated compensation capacitors. The one or more segmented sense devices are configured to provide pole-zero compensation based on output current. Further, the current range of each segment can be overlapped. As a result, the stability of the low drop-out regulator is not dependent upon the output current requirements or the capacitance requirements of the downstream circuit.

Abstract: A charge pump circuit is configured for charging of parasitic capacitances associated with charge pump capacitors in a manner that minimizes voltage ripple. The charge pump circuit is suitably configured with an independent charging circuit configured for supplying the current needed to charge the parasitic capacitances, rather than utilizing the reservoir capacitor to supply the needed current. The independent charging circuit can be implemented with various configurations of charge pump circuits, such as single phase or dual phase charge pumps, and/or doubler, tripler or inverter configurations. The independent charging circuit comprises a parasitic charging capacitor or other voltage source configured with one or more switch devices configured to facilitate charging of the parasitics during any phases of operation of the charge pump circuit.

Abstract: An output stage compensation circuit and method for a low drop-out regulator configured to facilitate stable operation while providing output voltage and current to downstream circuit devices is provided. An exemplary low drop-out regulator is configured with an output stage compensation circuit comprising one or more segmented sense devices configured to drive one or more fixed current sources. Each segmented sense device is configured to compensate a suitable range of output current and to multiply the effect of associated compensation capacitors. The one or more segmented sense devices are configured to provide pole-zero compensation based on output current. Further, the current range of each segment can be overlapped. As a result, the stability of the low drop-out regulator is not dependent upon the output current requirements or the capacitance requirements of the downstream circuit.