Patents by Inventor Rodney Virgil Bowman
Rodney Virgil Bowman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9424129Abstract: Methods and systems that include receiving data to be written to a NAND array in a controller; and writing the data to the NAND array, the NAND array including both type A NAND cells and type B NAND cells, wherein the type A NAND cells and the type B NAND cells have at least one structural difference.Type: GrantFiled: April 24, 2014Date of Patent: August 23, 2016Assignee: Seagate Technology LLCInventors: Young Pil Kim, Antoine Khoueir, Rodney Virgil Bowman
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Patent number: 9378830Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, data are written to a set of solid-state non-volatile memory cells so that each memory cell in the set is written to an associated initial programmed state. Drift in the programmed state of a selected memory cell in the set is detected, and the selected memory cell is partially reprogrammed to return the selected memory cell to the associated initial programmed state.Type: GrantFiled: July 16, 2013Date of Patent: June 28, 2016Assignee: Seagate Technology LLCInventors: Antoine Khoueir, Varun Voddi, Rodney Virgil Bowman
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Patent number: 9342399Abstract: A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A VT offset error differential is calculated. The VT offset error differential is a difference between a number of errors of the predominant type at a first VT offset and a number of errors of the predominant type at a second VT offset. A VT offset is determined using a ratio of the error type differential and the VT offset error differential.Type: GrantFiled: March 2, 2015Date of Patent: May 17, 2016Assignee: SEAGATE TECHNOLOGY LLCInventors: Mai A. Ghaly, Rodney Virgil Bowman
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Patent number: 9330790Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with various embodiments, a first data access operation is conducted on a memory cell and a first temperature associated with the memory cell and associated with the first data access operation is measured. A second temperature associated with the memory cell is measured. At least one operational parameter is adjusted responsive to the first and second temperatures associated with the memory cell. A second data access operation is conducted on the memory cell using the adjusted operational parameter.Type: GrantFiled: April 25, 2014Date of Patent: May 3, 2016Assignee: Seagate Technology LLCInventors: Young Pil Kim, Rodney Virgil Bowman, Caitlin Marie Race, Don R. Bloyer
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Patent number: 9231086Abstract: Memory arrays that include a first memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate; and a second memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate, wherein the first memory cell and the second memory cell are positioned parallel to each other.Type: GrantFiled: April 29, 2014Date of Patent: January 5, 2016Assignee: Seagate Technology LLCInventors: Antoine Khoueir, YoungPil Kim, Rodney Virgil Bowman
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Publication number: 20150310938Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with various embodiments, a first data access operation is conducted on a memory cell and a first temperature associated with the memory cell and associated with the first data access operation is measured. A second temperature associated with the memory cell is measured. At least one operational parameter is adjusted responsive to the first and second temperatures associated with the memory cell. A second data access operation is conducted on the memory cell using the adjusted operational parameter.Type: ApplicationFiled: April 25, 2014Publication date: October 29, 2015Applicant: Seagate Technology LLCInventors: Young Pil Kim, Rodney Virgil Bowman, Caitlin Marie Race, Don R. Bloyer
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Publication number: 20150310937Abstract: Methods and systems that include receiving data to be written to a NAND array in a controller; and writing the data to the NAND array, the NAND array including both type A NAND cells and type B NAND cells, wherein the type A NAND cells and the type B NAND cells have at least one structural difference.Type: ApplicationFiled: April 24, 2014Publication date: October 29, 2015Inventors: Young Pil Kim, Antoine Khoueir, Rodney Virgil Bowman
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Patent number: 9164830Abstract: A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits.Type: GrantFiled: January 14, 2014Date of Patent: October 20, 2015Assignee: SEAGATE TECHNOLOGY LLCInventors: Navneeth Kankani, Mark Allen Gaertner, Rodney Virgil Bowman, Ryan James Goss, David Scott Seekins, Tong Shirh Stone
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Patent number: 9123640Abstract: A memory device includes a stack of layers comprising a plurality of alternating layers of continuous electrically conductive material word line layers with layers of continuous electrically insulating material. A plurality of vias vertically extend through the stack of layers and a vertical bit line is disposed within each via. A layer of switching material separates the vertical bit line from the stack of layers, thereby forming an array of RRAM cells.Type: GrantFiled: May 13, 2013Date of Patent: September 1, 2015Assignee: Seagate Technology LLCInventors: Antoine Khoueir, YoungPil Kim, Rodney Virgil Bowman
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Patent number: 9122626Abstract: Threshold voltage offsets for threshold voltages are determined. The threshold voltage offsets may be linearly related by a non-zero slope. The threshold voltages are shifted using their respective threshold voltage offsets. The threshold voltages that are shifted by their respective threshold voltage offsets are used to read data from multi-level memory cells.Type: GrantFiled: May 13, 2013Date of Patent: September 1, 2015Assignee: SEAGATE TECHNOLOGY LLCInventors: Young-Pil Kim, Rodney Virgil Bowman
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Patent number: 9105361Abstract: A fault tolerant control line configuration useful in a variety of solid state memories such as but not limited to a flash memory. In accordance with some embodiments, an apparatus includes a plurality of memory cells, and a fault tolerant control line. The control line has an elongated first conductive path connected to each of the plurality of memory cells. An elongated second conductive path is disposed in a parallel, spaced apart relation to the first conductive path. A plurality of conductive support members are interposed between the first and second conductive paths to support the second conductive path above the first conductive path.Type: GrantFiled: October 31, 2012Date of Patent: August 11, 2015Assignee: Seagate Technology LLCInventors: YoungPil Kim, Rodney Virgil Bowman
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Patent number: 9099185Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a memory cell is provided with a plurality of available programming states to accommodate multi-level cell (MLC) programming. A control circuit stores a single bit logical value to the memory cell using single level cell (SLC) programming to provide a first read margin between first and second available programming states. The control circuit subsequently stores a single bit logical value to the memory cell using virtual multi-level cell (VMLC) programming to provide a larger, second read margin between the first available programming state and a third available programming state.Type: GrantFiled: December 20, 2013Date of Patent: August 4, 2015Assignee: Seagate Technology LLCInventors: YoungPil Kim, Rodney Virgil Bowman, Dadi Setiadi, Wei Tian
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Publication number: 20150178148Abstract: A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A VT offset error differential is calculated. The VT offset error differential is a difference between a number of errors of the predominant type at a first VT offset and a number of errors of the predominant type at a second VT offset. A VT offset is determined using a ratio of the error type differential and the VT offset error differential.Type: ApplicationFiled: March 2, 2015Publication date: June 25, 2015Inventors: Mai A. Ghaly, Rodney Virgil Bowman
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Publication number: 20150179268Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a memory cell is provided with a plurality of available programming states to accommodate multi-level cell (MLC) programming. A control circuit stores a single bit logical value to the memory cell using single level cell (SLC) programming to provide a first read margin between first and second available programming states. The control circuit subsequently stores a single bit logical value to the memory cell using virtual multi-level cell (VMLC) programming to provide a larger, second read margin between the first available programming state and a third available programming state.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Applicant: Seagate Technology LLCInventors: YoungPil Kim, Rodney Virgil Bowman, Dadi Setiadi, Wei Tian
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Patent number: 9037624Abstract: The disclosure is related systems and methods for using operation durations of a data storage medium to generate random numbers. In one embodiment, a device may comprise a random number generator circuit configured to store a value representing a duration of an operation on the data storage medium, and generate a random number based on the value. Another embodiment may be a method comprising recording durations of access operations to a data storage medium, and generating a random number based on the durations.Type: GrantFiled: August 3, 2012Date of Patent: May 19, 2015Assignee: Seagate Technology LLCInventors: Laszlo Hars, Monty Aaron Forehand, Donald Preston Matthews, Tong Shirh Stone, Navneeth Kankani, Rodney Virgil Bowman
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Patent number: 9001578Abstract: Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a soft erasure is performed on a block of memory cells by toggling an erasure status value without otherwise affecting a written state of the cells in the block. The memory cells are subsequently overwritten with a set of data using a write polarity direction determined responsive to the toggled erasure status value.Type: GrantFiled: September 11, 2012Date of Patent: April 7, 2015Assignee: Seagate Technology LLCInventors: YoungPil Kim, Dadi Setiadi, Wei Tian, Antoine Khoueir, Rodney Virgil Bowman
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Patent number: 8971111Abstract: A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A VT offset error differential is calculated. The VT offset error differential is a difference between a number of errors of the predominant type at a first VT offset and a number of errors of the predominant type at a second VT offset. A VT offset is determined using a ratio of the error type differential and the VT offset error differential.Type: GrantFiled: May 23, 2013Date of Patent: March 3, 2015Assignee: Seagate Technology LLCInventors: Mai A. Ghaly, Rodney Virgil Bowman
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Publication number: 20150023097Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, data are written to a set of solid-state non-volatile memory cells so that each memory cell in the set is written to an associated initial programmed state. Drift in the programmed state of a selected memory cell in the set is detected, and the selected memory cell is partially reprogrammed to return the selected memory cell to the associated initial programmed state.Type: ApplicationFiled: July 16, 2013Publication date: January 22, 2015Inventors: Antoine Khoueir, Varun Voddi, Rodney Virgil Bowman
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Publication number: 20150011062Abstract: Memory arrays that include a first memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate; and a second memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate, wherein the first memory cell and the second memory cell are positioned parallel to each other.Type: ApplicationFiled: April 29, 2014Publication date: January 8, 2015Applicant: SEAGATE TECHNOLOGY LLCInventors: Antoine Khoueir, YoungPil Kim, Rodney Virgil Bowman
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Publication number: 20140347923Abstract: A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A VT offset error differential is calculated. The VT offset error differential is a difference between a number of errors of the predominant type at a first VT offset and a number of errors of the predominant type at a second VT offset. A VT offset is determined using a ratio of the error type differential and the VT offset error differential.Type: ApplicationFiled: May 23, 2013Publication date: November 27, 2014Applicant: SEAGATE TECHNOLOGY LLCInventors: Mai A. Ghaly, Rodney Virgil Bowman