Abstract: Certain aspects of the present disclosure support techniques for collecting system information in a network on a chip (NoC). A dedicated packet may be transmitted from a source node to a destination node. As it traverses through the NoC, the dedicated packet may collect information from various nodes, which may be made available by the destination node. The collected information may be used in an effort to detect failures and collect statistics regarding the NoC.

Abstract: Certain aspects of the present disclosure support techniques for collecting system information in a network on a chip (NoC). A dedicated packet may be transmitted from a source node to a destination node. As it traverses through the NoC, the dedicated packet may collect information from various nodes, which may be made available by the destination node. The collected information may be used in an effort to detect failures and collect statistics regarding the NoC.

Abstract: A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives the index from the index generator and outputs a stored data value from a location indicated by the index. A compare circuit receives the data value from the memory and compares the data value and the search value to generate a match signal indicative of whether the data value and search value match. The match signal and index are output from the CAM device.

Abstract: A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives the index from the index generator and outputs a stored data value from a location indicated by the index. A compare circuit receives the data value from the memory and compares the data value and the search value to generate a match signal indicative of whether the data value and search value match. The match signal and index are output from the CAM device.

Abstract: A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives the index from the index generator and outputs a stored data value from a location indicated by the index. A compare circuit receives the data value from the memory and compares the data value and the search value to generate a match signal indicative of whether the data value and search value match. The match signal and index are output from the CAM device.

Abstract: The present invention provides a system and method for performing precharge timing verification on a logic circuit comprising a plurality of cascaded logic blocks, where in each logic block is implemented via a dynamic logic gate characterized by having a clock resettable output. In addition, a storage element is connected at each input to the logic circuit. The method of the present invention includes the following steps: preconditioning the storage elements so that all the inputs to the logic circuit are driven high when the clock goes high; transitioning the clock high so as to drive all the inputs of the logic circuit high, thereby driving all the outputs of the logic circuit high and discharging the storage node of each logic block; transitioning the clock low to precharge the storage node of all the logic blocks in the logic circuit, and thereby driving all the outputs low; and determining the longest precharge path in the logic circuit.

Abstract: Method and apparatus for bounding alignment shifts to enable at-speed denormalized result generation in an FMAC (fused multiply accumulate unit; also known as a multiply-add-fused floating-point unit, or MAF/FPU). The method and apparatus force a one into an FMAC's (leading bit anticipator) at a point which is determined to yield proper alignment of a potential denormalized result (denorm result). The precise location of the forced one is determined through a comparison of the FMAC's operand exponents. If the FMAC result is indeed a denorm, the shifter will only shift up to the position of the forced one, thereby leaving the exponent at zero and producing an FMAC result with a denormalized mantissa.