Abstract: An exemplary system and method for providing differential adjustment of the height of a multilayer substrate in localized areas for improved Q-factor performance of RF devices is disclosed as comprising inter alia: a multilayer substrate (200); an RF component (210) embedded in the substrate (200); a surface mounted component (220); and an RF shield (260) disposed next to the surface mounted component (220), wherein the height of the shield (260) does not extend substantially beyond the height of the surface mounted component (220). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize Q, RF performance and/or material characteristics.

Abstract: An exemplary system and method for providing differential adjustment of the height of a multilayer substrate in localized areas for improved Q-factor performance of RF devices is disclosed as comprising inter alia: a multilayer substrate (200); an RF component (210) embedded in the substrate (200); a surface mounted component (220); and an RF shield (260) disposed next to the surface mounted component (220), wherein the height of the shield (260) does not extend substantially beyond the height of the surface mounted component (220). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize Q, RF performance and/or material characteristics.

Abstract: An exemplary system and method for providing differential adjustment of the height of a multilayer substrate in localized areas for improved Q-factor performance of RF devices is disclosed as comprising inter alia: a multilayer substrate (200); an RF component (210) embedded in the substrate (200); a surface mounted component (220); and an RF shield (260) disposed next to the surface mounted component (220), wherein the height of the shield (260) does not extend substantially beyond the height of the surface mounted component (220). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize Q, RF performance and/or material characteristics.

Abstract: An exemplary system and method for minimizing degradation effects attributed to misalignment in the production of multilayer balun devices is disclosed as comprising inter alia any combination of coupled line folding that effectively provides a degenerate or otherwise reducible representation of line segment components wherein at least about half of the line segments (by, for example, linear distance or by line volume) are substantially orthogonal to the remaining half.

Abstract: An exemplary system and method for providing differential adjustment of the height of a multilayer substrate in localized areas for improved Q-factor performance of RF devices is disclosed as comprising inter alia: a multilayer substrate (200); an RF component (210) embedded in the substrate (200); a surface mounted component (220); and an RF shield (260) disposed next to the surface mounted component (220), wherein the height of the shield (260) does not extend substantially beyond the height of the surface mounted component (220). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize Q, RF performance and/or material characteristics.

Abstract: An exemplary system and method for minimizing degradation effects attributed to misalignment in the production of multilayer balun devices is disclosed as comprising inter alia any combination of coupled line folding that effectively provides a degenerate or otherwise reducible representation of line segment components wherein at least about half of the line segments (by, for example, linear distance or by line volume) are substantially orthogonal to the remaining half.

Abstract: A field emission device (100) includes an electroplated structure (122) and an electron emitter (118). Electroplated structure (122) includes a base (124), which is disposed proximate to electron emitter (118) and is made from the same material from which electron emitter (118) is made. Electroplated structure (122) further includes an electroplating electrode (126), which is disposed on base (124), and an electroplated layer (128), which is disposed on electroplating electrode (126). A method for fabricating field emission device (100) includes a step of forming electron emitter (118) and further includes a step of forming base (124) during the step of forming electron emitter (118). The method further includes a step of completely encapsulating electron emitter (118) prior to a step of forming electroplated layer (128).

Abstract: A method for providing a gray scale in a field emission display (50) includes the step of providing a first driving pulse (214) having a pulse width equal to a pulse width separation (115) between the graphs (100, 200) of total charge response versus pulse width of a driving pulse for the non-ideal field emission display and the corresponding ideal field emission display. The pulse width separation (115) is the horizontal distance between the two graphs (100, 200) at a region wherein the two graphs (100, 200) are generally parallel. The pulse width, t.sub.n, of an nth driving pulse corresponding to an nth gray scale level is given by t.sub.n =t.sub.1 +[n-1]*[(t.sub.N -t.sub.1)/(N-1)], wherein t.sub.1 is the pulse width of the first driving pulse (214), N is the total number of gray scale levels, and t.sub.N is the pulse width of the Nth driving pulse.

Abstract: A field emission display (100) includes a dielectric layer (132) having a plurality of emitter wells (134), a plurality of electron emitters (136) disposed one each within the plurality of emitter wells (134), a plurality of conductive rows (138, 140, 142) disposed on the dielectric layer (132) and having sacrificial portions (154), an ion shield (139) disposed on the dielectric layer (132) and spaced apart from the sacrificial portions (154) of the plurality of conductive rows (138, 140, 142), and an anode (121) opposing the plurality of electron emitters (136) and defining a projected area (122) at the plurality of conductive rows (138, 140, 142). The sacrificial portions (154) of the plurality of conductive rows (138, 140, 142) extend beyond the projected area (122) of the anode (121).

Abstract: A low subthreshold leakage current, p-channel HFET including a GaAs supporting substrate with a first GaAs buffer layer and a first Al.sub.0.75 Ga.sub.0.25 As diffusion barrier layer formed thereon and a low temperature grown layer, including one of GaAs and AlGaAs, grown at 200.degree. C. on the first diffusion barrier layer. A second Al.sub.0.75 Ga.sub.0.25 As diffusion barrier layer is positioned on the low temperature grown layer and a second GaAs buffer layer is grown on the second diffusion barrier layer. A p-channel HFET is formed on the second buffer layer.

Abstract: A charge dissipation field emission device (200, 300, 400) includes a supporting substrate (210, 310, 410), a cathode (215, 315, 415) formed thereon, a dielectric layer (240, 340, 440) formed on the cathode (215, 315, 415) and having emitter wells (260, 360, 460) and a charge dissipation well (252, 352, 452, 453) exposing a charge-collecting surface (248, 348, 448, 449), for bleeding off gaseous positive charge generated during the operation of the charge dissipation field emission device (200, 300, 400), an electron emitter (270, 370, 470) formed in each of the emitter wells (260, 360, 460), and an anode (280, 380, 480) spaced from the dielectric layer (240, 340, 440) for collecting electrons emitted by the electron emitters (270, 370, 470).

Abstract: A field emission device (100, 200) includes an anode (190); a substrate (110); a plurality of spaced apart cathodes (120); a dielectric layer (124) disposed on the cathodes (120); a plurality of spacer pads (130, 230) disposed on the substrate (110) between adjacent cathodes (120) and including a spacer contact layer (142, 185) that defines the surfaces of the spacer pads (130, 230); a spacer (150) having a first edge (157), a second edge (155), and a conductive layer (152) disposed on the second edge (155), the first edge (157) contacting the anode (190), the conductive layer (152) contacting the spacer contact layer (142, 185) at the spacer pads (130, 230); and an electron emitter (170) disposed within the dielectric layer (124) and spaced apart from the second edge (155) of the spacer (150).

Abstract: An N-type HIGFET (10) utilizes two etch layers (17,18) to form a gate insulator (16) to be shorter that the gate electrode (21). This T-shaped gate structure facilitates forming source (23) and drain (24) regions that are separated from the gate insulator (16) by a distance (22) in order to reduce leakage current and increase the breakdown voltage.

Abstract: A HIGFET (10) utilizes an etch stop layer (17) to form a gate insulator (16) to be narrower than the gate electrode (21). This T-shaped gate structure facilitates forming source (23) and drain (24) regions that are separated from the gate insulator (16) by a distance (22) in order to reduce leakage current and increase the breakdown voltage.

Abstract: An N-type HIGFET (10) utilizes two etch layers (17,18) to form a gate insulator (16) to be shorter that the gate electrode (21). This T-shaped gate structure facilitates forming source (23) and drain (24) regions that are separated from the gate insulator (16) by a distance (22) in order to reduce leakage current and increase the breakdown voltage.