Abstract: Compile-time recognition of graph structure where graph has arbitrary connectivity and is constructed using recursive computations is provided. In one aspect, the graph structure recognized at compile time may be duplicated at runtime and can then operate on runtime values not known at compile time.

Abstract: Extraction of functional semantics and isolated dataflow from imperative object oriented languages, in one aspect, may include identifying one or more methods and/or classes associated with one or more of a plurality of property labels in a computer code written in object oriented language to extract functional and isolation characteristics in the computer code. The plurality of property labels supported by one or more checking rules, are used to verify that the one or more methods and/or classes identified with the plurality of property labels have isolation characteristics. An object oriented language compiler is provided for supplying the plurality of property labels and checking rules. The object oriented language compiler further may include capability to transform methods into compute tasks and connect the compute tasks so as to create a dataflow graph.

Abstract: Extraction of functional semantics and isolated dataflow from imperative object oriented languages, in one aspect, may include identifying one or more methods and/or classes associated with one or more of a plurality of property labels in a computer code written in object oriented language to extract functional and isolation characteristics in the computer code. The plurality of property labels supported by one or more checking rules, are used to verify that the one or more methods and/or classes identified with the plurality of property labels have isolation characteristics. An object oriented language compiler is provided for supplying the plurality of property labels and checking rules. The object oriented language compiler further may include capability to transform methods into compute tasks and connect the compute tasks so as to create a dataflow graph.

Abstract: A communication stack for software-hardware co-execution on heterogeneous computing systems with processors and reconfigurable logic, in one aspect, may comprise a crossbar operable to connect hardware user code and functioning as a platform independent communication layer. A physical interface interfaces to the reconfigurable logic. A physical interface bridge is connected to the cross and the physical interface. The physical interface bridge connects the crossbar and the physical interface via a platform specific translation layer specific to the reconfigurable logic. The crossbar, the physical interface, and the physical interface bridge may be instantiated in response to the hardware user code being generated, the crossbar instantiated with associated parameters comprising one or more routes and associated data widths. The hardware user code is assigned a unique virtual route in the crossbar.

Abstract: A communication stack for software-hardware co-execution on heterogeneous computing systems with processors and reconfigurable logic, in one aspect, may comprise a crossbar operable to connect hardware user code and functioning as a platform independent communication layer. A physical interface interfaces to the reconfigurable logic. A physical interface bridge is connected to the cross and the physical interface. The physical interface bridge connects the crossbar and the physical interface via a platform specific translation layer specific to the reconfigurable logic. The crossbar, the physical interface, and the physical interface bridge may be instantiated in response to the hardware user code being generated, the crossbar instantiated with associated parameters comprising one or more routes and associated data widths. The hardware user code is assigned a unique virtual route in the crossbar.

Abstract: The present disclosure relates generally to the field of automatic conversion of sequential array-based programs to parallel MapReduce programs. In various examples, automatic conversion of sequential array-based programs to parallel MapReduce programs may be implemented in the form of systems, methods and/or algorithms.

Abstract: The present disclosure relates generally to the field of automatic conversion of sequential array-based programs to parallel MapReduce programs. In various examples, automatic conversion of sequential array-based programs to parallel MapReduce programs may be implemented in the form of systems, methods and/or algorithms.

Abstract: Converting data transformations entered in a spreadsheet program into a circuit representation of those transformations. The circuit representation can run independently of the spreadsheet program to transform input data into output data. In some cases the circuit representation is in the form of hardware, accepts and/or produces data streams, and/or the circuit and/or output data or data streams can be shared among multiple users and/or subscribers. Where data streams are processed, the transformations may include well-specified timing semantics, supporting operations that involve rate-based rate manipulation, value-based rate manipulation, and/or access to past cell values.

Abstract: Compile-time recognition of graph structure where graph has arbitrary connectivity and is constructed using recursive computations is provided. In one aspect, the graph structure recognized at compile time may be duplicated at runtime and can then operate on runtime values not known at compile time.

Abstract: Compile-time recognition of graph structure where graph has arbitrary connectivity and is constructed using recursive computations is provided. In one aspect, the graph structure recognized at compile time may be duplicated at runtime and can then operate on runtime values not known at compile time.

Abstract: Compile-time recognition of graph structure where graph has arbitrary connectivity and is constructed using recursive computations is provided. In one aspect, the graph structure recognized at compile time may be duplicated at runtime and can then operate on runtime values not known at compile time.

Abstract: A technique for compiling and running high-level program on heterogeneous computers may include partitioning a program code into two or more logical units, and compiling each of the logical units into one or more executable entities. At least some of the logical units are compiled into two or more executable entities, the two or more executable entities being different compilations of the same logical unit. The two or more executable entities are compatible to run on respective two or more platforms that have different architecture.

Abstract: Compile-time recognition of graph structure where graph has arbitrary connectivity and is constructed using recursive computations is provided. In one aspect, the graph structure recognized at compile time may be duplicated at runtime and can then operate on runtime values not known at compile time.

Abstract: Compile-time recognition of graph structure where graph has arbitrary connectivity and is constructed using recursive computations is provided. In one aspect, the graph structure recognized at compile time may be duplicated at runtime and can then operate on runtime values not known at compile time.

Abstract: A communication stack for software-hardware co-execution on heterogeneous computing systems with processors and reconfigurable logic, in one aspect, may comprise a crossbar operable to connect hardware user code and functioning as a platform independent communication layer. A physical interface interfaces to the reconfigurable logic. A physical interface bridge is connected to the cross and the physical interface. The physical interface bridge connects the crossbar and the physical interface via a platform specific translation layer specific to the reconfigurable logic. The crossbar, the physical interface, and the physical interface bridge may be instantiated in response to the hardware user code being generated, the crossbar instantiated with associated parameters comprising one or more routes and associated data widths. The hardware user code is assigned a unique virtual route in the crossbar.

Abstract: A communication stack for software-hardware co-execution on heterogeneous computing systems with processors and reconfigurable logic, in one aspect, may comprise a crossbar operable to connect hardware user code and functioning as a platform independent communication layer. A physical interface interfaces to the reconfigurable logic. A physical interface bridge is connected to the cross and the physical interface. The physical interface bridge connects the crossbar and the physical interface via a platform specific translation layer specific to the reconfigurable logic. The crossbar, the physical interface, and the physical interface bridge may be instantiated in response to the hardware user code being generated, the crossbar instantiated with associated parameters comprising one or more routes and associated data widths. The hardware user code is assigned a unique virtual route in the crossbar.

Abstract: A technique for compiling and running high-level program on heterogeneous computers may include partitioning a program code into two or more logical units, and compiling each of the logical units into one or more executable entities. At least some of the logical units are compiled into two or more executable entities, the two or more executable entities being different compilations of the same logical unit. The two or more executable entities are compatible to run on respective two or more platforms that have different architecture.

Abstract: Searching for desired clock frequency for integrated circuit-based design may receive timing result of a hardware synthesis job executed based on a code specifying hardware design. One or more different timing constraints specifying respective one or more different clock frequencies than used in the hardware synthesis job may be automatically generated without modifying the code. One or more instances of the hardware synthesis job to run with the respective one or more different timing constraints may be automatically spawned. The automatic generation and spawning may repeat until a termination criterion is met, and/or a desired successful timing constraint is identified for the hardware design from the different timing constraints based on whether the one or more instances of the hardware synthesis job met their respective timing constraints.

Abstract: Searching for desired clock frequency for integrated circuit-based design may receive timing result of a hardware synthesis job executed based on a code specifying hardware design. One or more different timing constraints specifying respective one or more different clock frequencies than used in the hardware synthesis job may be automatically generated without modifying the code. One or more instances of the hardware synthesis job to run with the respective one or more different timing constraints may be automatically spawned. The automatic generation and spawning may repeat until a termination criterion is met, and/or a desired successful timing constraint is identified for the hardware design from the different timing constraints based on whether the one or more instances of the hardware synthesis job met their respective timing constraints.

Abstract: Searching for desired clock frequency for integrated circuit-based design may receive timing result of a hardware synthesis job executed based on a code specifying hardware design. One or more different timing constraints specifying respective one or more different clock frequencies than used in the hardware synthesis job may be automatically generated without modifying the code. One or more instances of the hardware synthesis job to run with the respective one or more different timing constraints may be automatically spawned. The automatic generation and spawning may repeat until a termination criterion is met, and/or a desired successful timing constraint is identified for the hardware design from the different timing constraints based on whether the one or more instances of the hardware synthesis job met their respective timing constraints.