Patents by Inventor Rodrick J. Hendricks

Rodrick J. Hendricks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11784150
    Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: October 10, 2023
    Assignee: Intel Corporation
    Inventors: Dae-Woo Kim, Ajay Jain, Neha M. Patel, Rodrick J. Hendricks, Sujit Sharan
  • Publication number: 20220285306
    Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.
    Type: Application
    Filed: May 26, 2022
    Publication date: September 8, 2022
    Inventors: Dae-Woo KIM, Ajay JAIN, Neha M. PATEL, Rodrick J. HENDRICKS, Sujit SHARAN
  • Patent number: 11380643
    Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Dae-Woo Kim, Ajay Jain, Neha M. Patel, Rodrick J. Hendricks, Sujit Sharan
  • Publication number: 20200402940
    Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 24, 2020
    Inventors: Dae-Woo KIM, Ajay JAIN, Neha M. PATEL, Rodrick J. HENDRICKS, Sujit SHARAN
  • Patent number: 10797014
    Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Dae-Woo Kim, Ajay Jain, Neha M. Patel, Rodrick J. Hendricks, Sujit Sharan
  • Publication number: 20190157232
    Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.
    Type: Application
    Filed: August 16, 2016
    Publication date: May 23, 2019
    Inventors: Dae-Wood Kim, Ajay Jain, Neha M. Patel, Rodrick J. Hendricks, Sujit Sharan