Patents by Inventor Rodrigo Cordero

Rodrigo Cordero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8588406
    Abstract: A portion of data is obfuscated by performing a bitwise XOR function between bits of the data portion and bits of a mask. The mask is generated based on the memory address of the data portion. A bitfield representing the memory address of the data portion is split into subset bitfields. Each subset then forms the input of a corresponding primary randomizing unit. Each primary randomizing unit is arranged to generate an output bitfield that appears to be randomly correlated with the input, but which may be determined from the input if certain secret information is known. The output of the primary randomizing units is input into a series of secondary randomizing units. Each secondary randomizing unit is arranged to input at least one bit of the output of every primary randomizing unit. The output of the secondary randomizing units are then combined by concatenation to form a data mask.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: November 19, 2013
    Assignee: STMicroelectronics Limited
    Inventors: Andrew Dellow, Rodrigo Cordero
  • Patent number: 8458761
    Abstract: A receiver for receiving a data stream comprises a filtering arrangement for filtering said received data stream and a processor. The filtering arrangement is arranged to load at least a part of said data stream, to filter at least part of said data stream and to read at least part of said data stream. The filtering arrangement has a first mode in which said steps are carried out and a second mode in which said processor is arranged to interrupt the steps carried out by said filtering arrangement.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: June 4, 2013
    Assignee: STMicroelectronics Limited
    Inventors: Rodrigo Cordero, Patrice Woodward
  • Patent number: 8191125
    Abstract: An embodiment comprises a semiconductor integrated circuit for restricting the rate at which data may be accessed from an external memory by a device coupled to the circuit. The rate of data access is restricted if the data access satisfies one or more conditions. For example, one of the conditions is that the device which is requesting the data is insecure. Another condition is that the requested data is privileged. A data access monitor is provided to monitor data accesses and to is arranged to generate an access signal to indicate whether the conditions are satisfied or not. A bandwidth comparator determines whether data access exceeds a threshold and, if so, the semiconductor integrated circuit is impaired to prevent further data access.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: May 29, 2012
    Assignee: STMicroelectronics Limited
    Inventors: Andrew Dellow, Rodrigo Cordero
  • Patent number: 7969972
    Abstract: A system including input circuitry for receiving from one of a plurality of sources at least one packet stream including a plurality of packets for providing audio, video, private data and/or associated information; at least one output for outputting at least one packet of the at least one packet stream to circuitry arranged to provide an output stream; wherein the system is arranged to provide a tag indicative of the source, the tag being associated with the at least one packet.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: June 28, 2011
    Assignee: STMicroelectronics (R&D) Ltd.
    Inventors: Rodrigo Cordero, Paul Cox, Andrew Dellow
  • Patent number: 7889862
    Abstract: A memory stores data in an encrypted form. A modifiable register stores a memory address, a0, defining a boundary separating the memory into two regions. The lower region stores data encrypted using a key B, and the upper region stores data encrypted using a different key A. Data stored on the boundary address is encrypted using key A. Accordingly, when data is read from a memory address a, key A is used to decrypt the data if a?a0, and key B is used if a<a0. However, when data is written to a memory address a, then key A is used to encrypt the data if a?a0+1, key B is used if a<a0+1. When data is written to the boundary address, a0, the position of the boundary is caused to increase by one unit.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: February 15, 2011
    Assignee: STMicroelectronics Limited
    Inventors: Andrew Dellow, Peter Bennett, Rodrigo Cordero
  • Patent number: 7839937
    Abstract: Circuitry for processing data includes a plurality of filters arranged in parallel. Input data is stored. The input data is applied to the plurality of filters to provide at least two parallel results. An operation is carried out with respect to the results.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: November 23, 2010
    Assignee: STMicroelectronics Limited
    Inventors: Rodrigo Cordero, Patrice Woodward
  • Patent number: 7836300
    Abstract: A semiconductor integrated circuit for the processing of conditional access television signals, the circuit including an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. Control signals broadcast with the television signals include control words and common keys. The common keys are received in encrypted form, encrypted according to a secret key unique to each semiconductor integrated circuit. The input interface is connected to a decryption circuit whereby the only manner of providing the common keys to the circuit are in encrypted form encrypted according to the secret key. Due to the monolithic nature of the circuit, no secrets are exposed and the system is secure.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: November 16, 2010
    Assignee: STMicroelectronics Limited
    Inventors: Andrew Dellow, Rodrigo Cordero
  • Publication number: 20070121943
    Abstract: A portion of data is obfuscated by performing a bitwise XOR function between bits of the data portion and bits of a mask. The mask is generated based on the memory address of the data portion. A bitfield representing the memory address of the data portion is split into subset bitfields. Each subset then forms the input of a corresponding primary randomizing unit. Each primary randomizing unit is arranged to generate an output bitfield that appears to be randomly correlated with the input, but which may be determined from the input if certain secret information is known. The output of the primary randomizing units is input into a series of secondary randomizing units. Each secondary randomizing unit is arranged to input at least one bit of the output of every primary randomizing unit. The output of the secondary randomizing units are then combined by concatenation to form a data mask.
    Type: Application
    Filed: September 18, 2006
    Publication date: May 31, 2007
    Applicant: STMicroelectronics Limited
    Inventors: Andrew Dellow, Rodrigo Cordero
  • Publication number: 20070124811
    Abstract: A memory stores data in an encrypted form. A modifiable register stores a memory address, a0, defining a boundary separating the memory into two regions. The lower region stores data encrypted using a key B, and the upper region stores data encrypted using a different key A. Data stored on the boundary address is encrypted using key A. Accordingly, when data is read from a memory address a, key A is used to decrypt the data if a?a0, and key B is used if a<a0. However, when data is written to a memory address a, then key A is used to encrypt the data if a?a0+1, key B is used if a<a0+1. When data is written to the boundary address, a0, the position of the boundary is caused to increase by one unit.
    Type: Application
    Filed: September 18, 2006
    Publication date: May 31, 2007
    Applicant: STMicroelectronics Limited
    Inventors: Andrew Dellow, Peter Bennett, Rodrigo Cordero
  • Publication number: 20050276264
    Abstract: A system including input circuitry for receiving from one of a plurality of sources at least one packet stream including a plurality of packets for providing audio, video, private data and/or associated information; at least one output for outputting at least one packet of the at least one packet stream to circuitry arranged to provide an output stream; wherein the system is arranged to provide a tag indicative of the source, the tag being associated with the at least one packet.
    Type: Application
    Filed: June 3, 2005
    Publication date: December 15, 2005
    Applicant: STMicroelectronics Limited
    Inventors: Rodrigo Cordero, Paul Cox, Andrew Dellow
  • Publication number: 20050235308
    Abstract: An embodiment comprises a semiconductor integrated circuit for restricting the rate at which data may be accessed from an external memory by a device coupled to the circuit. The rate of data access is restricted if the data access satisfies one or more conditions. For example, one of the conditions is that the device which is requesting the data is insecure. Another condition is that the requested data is privileged. A data access monitor is provided to monitor data accesses and to is arranged to generate an access signal to indicate whether the conditions are satisfied or not. A bandwidth comparator determines whether data access exceeds a threshold and, if so, the semiconductor integrated circuit is impaired to prevent further data access.
    Type: Application
    Filed: December 17, 2004
    Publication date: October 20, 2005
    Applicant: STMicroelectronics Limited
    Inventors: Andrew Dellow, Rodrigo Cordero
  • Publication number: 20040156507
    Abstract: A semiconductor integrated circuit for the processing of conditional access television signals, the circuit including an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. Control signals broadcast with the television signals include control words and common keys. The common keys are received in encrypted form, encrypted according to a secret key unique to each semiconductor integrated circuit. The input interface is connected to a decryption circuit whereby the only manner of providing the common keys to the circuit are in encrypted form encrypted according to the secret key. Due to the monolithic nature of the circuit, no secrets are exposed and the system is secure.
    Type: Application
    Filed: November 10, 2003
    Publication date: August 12, 2004
    Applicant: STMicroelectronics Limited
    Inventors: Andrew Dellow, Rodrigo Cordero
  • Publication number: 20030076856
    Abstract: A receiver for receiving a data stream comprises a filtering arrangement for filtering said received data stream and a processor. The filtering arrangement is arranged to load at least a part of said data stream, to filter at least part of said data stream and to read at least part of said data stream. The filtering arrangement has a first mode in which said steps are carried out and a second mode in which said processor is arranged to interrupt the steps carried out by said filtering arrangement.
    Type: Application
    Filed: June 11, 2002
    Publication date: April 24, 2003
    Applicant: STMicroelectronics Limited
    Inventors: Rodrigo Cordero, Patrice Woodward
  • Publication number: 20020186775
    Abstract: The invention relates to circuitry for processing data. The circuitry comprises a plurality of filters arranged in parallel and means for storing input data. The input data is applied to the plurality of filters to provide at least two parallel results and means for carrying out an operation with respect to the results.
    Type: Application
    Filed: June 11, 2002
    Publication date: December 12, 2002
    Inventors: Rodrigo Cordero, Patrice Woodward
  • Publication number: 20020046370
    Abstract: Error checking circuitry for performing error checks based on mathematical functions comprises a data input stage adapted to receive incoming data and at least one feedback signal, a register arranged to receive at a plurality of register input signals from the data input stage and to generate at least one signal to feedback to the data input stage, and multiplexing circuitry, wherein the multiplexing circuitry is provided in association with the register such that signal routes through the register are configurable to successively perform error checks based on different first and second mathematical functions.
    Type: Application
    Filed: August 16, 2001
    Publication date: April 18, 2002
    Inventor: Rodrigo Cordero