Patents by Inventor Roee Moyal

Roee Moyal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12634240
    Abstract: Aspects of the present disclosure are directed to systems, methods, and computer readable media for dynamic data transfer rate control. One method includes alternating a network device between a plurality of supported data transfer rates that are supported by the network device to achieve an unsupported data transfer rate that is not supported by the network device. Another method includes adding one or more dummy work descriptors to a data stream, and transmitting the data stream including the one or more dummy work descriptors at a supported data transfer rate that is supported by a network device to achieve an effective unsupported data transfer rate that is not supported by the network device.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: May 19, 2026
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Natan Manevich, Dotan David Levi, Alex Vaynman, Roee Moyal, Alex Rosenbaum, Stanislav Raitsyn, Yuval Atias
  • Publication number: 20260005977
    Abstract: Devices, methods, and computer program products are provided for addressing out of order packet delivery in dynamically connected (DC) transport protocols. An example method includes receiving, by a destination device, a plurality of data packets from a transmitting device where each of the plurality of data packets includes a connect header associated with DC establishment and establishing a DC between the destination device and the transmitting device based on one or more of the data packets of the plurality of data packets. The plurality of data packets include a first set of data packets received by the destination device prior to establishment of the DC, and a second set of data packets received by the destination device after establishment of the DC. The establishment of the DC occurs irrespective of an order in which each of the plurality of data packets are received by the destination device.
    Type: Application
    Filed: June 27, 2024
    Publication date: January 1, 2026
    Applicant: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Yamin FRIEDMAN, Idan BURSTEIN, Diego CRUPNICOFF, Roee MOYAL
  • Publication number: 20260006096
    Abstract: Devices, methods, and computer program products are provided for duplicate delivery prevention for dynamically connected transport protocols. An example method includes receiving, by a destination device, a first data packet from a transmitting device that includes instructions for establishing a dynamic connection between the destination device and the transmitting device and establishing the dynamic connection between the destination device and the transmitting device based on the first data packet. The method further includes maintaining the dynamic connection between the destination device and the transmitting device for at least a threshold time period (T) defining a duration during which data packets are received by the destination device from the transmitting device.
    Type: Application
    Filed: June 27, 2024
    Publication date: January 1, 2026
    Applicant: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Yamin FRIEDMAN, Idan BURSTEIN, Ariel SHAHAR, Diego CRUPNICOFF, Roee MOYAL, Miriam MENES
  • Patent number: 12493547
    Abstract: Apparatuses, systems, and techniques for dynamic memory allocation using a shared free list. A user tag is received, and a hashed user tag is generated. A first reference to an entry in a second data structure is identified in a first data structure using the hashed user tag. The entry includes multiple user tags. Responsive to determining that the multiple user tags do not include the user tag, a memory address is identified in a third data structure. The memory address is removed from the third data structure. Memory is allocated for a user context associated with the user tag at the memory address. The user tag is added to the second data structure.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: December 9, 2025
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Gil Kremer, Roee Moyal, Igor Voks, Liel Peled, Eliel Peretz, Ariel Shahar
  • Publication number: 20250363044
    Abstract: A computing system includes a memory and a table remap circuit. The table remap circuit is to modify a size of a table comprising table elements stored in the memory, while the table is available for access by one or more users, by (i) defining a first interim table and a second interim table, (ii) iteratively transferring table elements from the first interim table to the second interim table, (iii) in response to a request from a user to write a table element in the table, writing the table element in the first interim table or in the second interim table in accordance with a selection criterion, and (iv) remapping the table to the second interim table.
    Type: Application
    Filed: May 27, 2024
    Publication date: November 27, 2025
    Inventors: Gil Kremer, Roee Moyal, Ariel Shahar
  • Publication number: 20250358219
    Abstract: Technologies for spreading packets of transport flows across multiple network paths are described. A network controller includes a transport layer and a network layer. The transport layer includes a flow scheduler to schedule a transport flow from one of a plurality of transport flows. The network layer includes multipath logic to receive packets from the transport flow and select which path of a plurality of paths to a destination to use for the packets based on path congestion weights corresponding to the plurality of paths.
    Type: Application
    Filed: June 2, 2025
    Publication date: November 20, 2025
    Inventors: Yamin Friedman, Idan Borshteen, Roee Moyal, Yuval Shpigelman
  • Publication number: 20250350671
    Abstract: Technologies for payload direct memory storing (PDMS) for out-of-order delivery of packets in remote direct memory access (RDMA) are described. A responder device includes an RDMA transport layer that can receive packets out of order and allow direct data placement of packet data in order. The responder device receives a first packet with a first packet number and first location information. The responder device stores first packet data to a first location according to the first location information. The responder device also receives a second packet and stores second packet data to a second location according to the second location information. A second packet number indicates that the first packet is received out of order. The first and second packet data are stored in order. The responder device can provide an indication that a message has arrived in response to determining that all packets of the message have arrived.
    Type: Application
    Filed: July 21, 2025
    Publication date: November 13, 2025
    Inventors: Yamin Friedman, Ariel Shahar, Idan Borshteen, Roee Moyal
  • Patent number: 12443690
    Abstract: A computing device which may include a hardware-configurable device reconfigurable to perform a series of logical operations to determine, based on parameters related to execution of a job received by the hardware-configurable device, whether or not the job is permissible for execution.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: October 14, 2025
    Assignee: Mellanox Technologies Ltd.
    Inventors: Dotan Finkelshtein, Roee Moyal, Igor Voks
  • Publication number: 20250286812
    Abstract: Technologies for spreading a burst of data across multiple network paths in remote direct memory access (RDMA) over converged Ethernet (ROCE) and InfiniBand are described. A RDMA adapter receives, from a requestor device over a local interface, a request to send data of a transport flow directed to a target device over a network interface, and one or more parameters being related to a multipath selection by the network controller. The RDMA adapter sends a first burst of data of the transport flow via a first network path to the target device. The RDMA adapter identifies, using the one or more parameters, a second network path to the target device. The RDMA adapter sends the second burst of data to the target device on the second network path.
    Type: Application
    Filed: May 12, 2025
    Publication date: September 11, 2025
    Inventors: Yamin Friedman, Idan Borshteen, Roee Moyal, Yuval Shpigelman
  • Publication number: 20250286823
    Abstract: In one embodiment, a responder device includes a network interface to receive packets of a stream of packets transmitted from a requester device with packet sequence numbers, and packet processing circuitry to collect information about the packet sequence numbers of the packets that have been received from the requester device, generate a selective acknowledgement including an indication of the packet sequence numbers of at least one packet of the packets that has been received and at least one other packet of the packets that has not been received by the responder device from the requester device, wherein the at least one packet that has been received by the responder device includes at least one of the packets received out-of-order according to the packet sequence numbers, and send the selective acknowledgement to the requester device via the network interface.
    Type: Application
    Filed: February 11, 2025
    Publication date: September 11, 2025
    Inventors: Yamin Friedman, Idan Borshteen, Ariel Shahar, Roee Moyal, Shay Aisman, Diego Crupnicoff, Yuval Shpigelman
  • Publication number: 20250286828
    Abstract: A network device includes a hardware-implemented packet processing pipeline includes: multiple pipeline stages, and a processor. The hardware-implemented packet processing pipeline is to process packets exchanged with a packet network. The processor is to execute sideband tasks for the packet processing pipeline. At least one of the pipeline stages is to trigger the processor to execute a sideband task by posting a Completion-Queue Element (CQE) on a Completion Queue (CQ) accessible to the processor.
    Type: Application
    Filed: March 2, 2025
    Publication date: September 11, 2025
    Inventors: Yuval Shpigelman, Elazar Cohen, Yamin Friedman, Ariel Shahar, Roee Moyal, Shay Aisman, Avi Urman, Doron Haim, Saar Tarnopolsky, Amir Sharaffy
  • Patent number: 12407766
    Abstract: Technologies for payload direct memory storing (PDMS) for out-of-order delivery of packets in remote direct memory access (RDMA) are described. A responder device includes an RDMA transport layer that can receive packets out of order and allow direct data placement of packet data in order. The responder device receives a first packet with a first packet number and first location information. The responder device stores first packet data to a first location according to the first location information. The responder device also receives a second packet and stores second packet data to a second location according to the second location information. A second packet number indicates that the first packet is received out of order. The first and second packet data are stored in order. The responder device can provide an indication that a message has arrived in response to determining that all packets of the message have arrived.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: September 2, 2025
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Yamin Friedman, Ariel Shahar, Idan Borshteen, Roee Moyal
  • Patent number: 12348410
    Abstract: Technologies for spreading packets of transport flows across multiple network paths are described. A network controller includes a transport layer and a network layer. The transport layer includes a flow scheduler to schedule a transport flow from one of a plurality of transport flows. The network layer includes multipath logic to receive packets from the transport flow and select which path of a plurality of paths to a destination to use for the packets based on path congestion weights corresponding to the plurality of paths.
    Type: Grant
    Filed: January 17, 2024
    Date of Patent: July 1, 2025
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Yamin Friedman, Idan Borshteen, Roee Moyal, Yuval Shpigelman
  • Patent number: 12323320
    Abstract: Technologies for spreading a burst of data across multiple network paths in remote direct memory access (RDMA) over converged Ethernet (RoCE) and InfiniBand are described. A network interface controller sends a first burst of a transport flow directed to a second node over a first network path. The network interface controller determines that a second burst is to be sent over a different network path, and identifies a second network path using a multipath context. The multipath context stores a first weight value or a first state associated with the first network path and a second weight value or a second state associated with the second network path. The network interface controller sends the second burst of data to the second node via the second network path.
    Type: Grant
    Filed: February 16, 2024
    Date of Patent: June 3, 2025
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Yamin Friedman, Idan Borshteen, Roee Moyal, Yuval Shpigelman
  • Patent number: 12316555
    Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry, and retrieve WRs from the multiple NSQs and execute data transmission operations specified in the WRs retrieved from the multiple NSQs.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: May 27, 2025
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Gal Yefet, Daniel Marcovitch, Roee Moyal, Ariel Shahar, Gil Bloch, Lior Narkis
  • Publication number: 20250165426
    Abstract: Devices, methods, and systems are provided. In one example, a device is described to include a device interface that receives data from at least one data source; a data shuffle unit that collects the data received from the at least one data source, receives a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, performs the data shuffle operation on the collected data to produce shuffled data, and provides the shuffled data to at least one data target.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Inventors: Daniel Marcovitch, Dotan David Levi, Eyal Srebro, Eliel Peretz, Roee Moyal, Richard Graham, Gil Bloch, Sean Pieper
  • Patent number: 12229072
    Abstract: Devices, methods, and systems are provided. In one example, a device is described to include a device interface that receives data from at least one data source; a data shuffle unit that collects the data received from the at least one data source, receives a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, performs the data shuffle operation on the collected data to produce shuffled data, and provides the shuffled data to at least one data target.
    Type: Grant
    Filed: March 7, 2024
    Date of Patent: February 18, 2025
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Daniel Marcovitch, Dotan David Levi, Eyal Srebro, Eliel Peretz, Roee Moyal, Richard Graham, Gil Bloch, Sean Pieper
  • Patent number: 12224950
    Abstract: In one embodiment, a system includes a memory to store a work queue including work queue entry slots, a processing device to write work queue entries to the work queue in a consecutive and cyclic manner, and a network device including a network interface to share packet over a network, and packet processing circuitry to read the work queue entries from the work queue in a consecutive and cyclic manner, the work queue entries indicating work to be performed associated with the packets, dequeue respective ones of the work queue entries read from the work queue responsively to reading the respective work queue entries from the work queue, add the work queue entries to an execution database used to track execution of the work queue entries, and execute the work queue entries in the execution database.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: February 11, 2025
    Assignee: Mellanox Technologies, Ltd
    Inventors: Gal Yefet, Daniel Marcovitch, Roee Moyal, Gil Bloch, Ariel Shahar, Yossef Itigin
  • Publication number: 20250028658
    Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and a packet processing circuitry operatively coupled to the network interface. The packet processing circuitry may receive, via the network interface, a message; retrieve, via a packet processing circuitry, a work queue element (WQE) index identifying a position of a WQE in a receive queue; determine that the message is associated with a small payload; process the message without consuming the WQE; receive, via the network interface, a subsequent message; and process the subsequent message using the WQE. In this way, the systems and methods describe herein reduce the latency in processing of the data packets.
    Type: Application
    Filed: July 20, 2023
    Publication date: January 23, 2025
    Inventors: Ortal Ben Moshe, Roee Moyal, Shay Aisman, Gil Bloch, Ariel Shahar, Roman Nudelman, Gil Kremer, Yossef Itigin, Lior Narkis
  • Publication number: 20250030649
    Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and packet processing circuitry operatively coupled to the network interface. The packet processing circuitry is configured to receive, via the network interface, a plurality of data packets associated with a message; determine, for each data packet, at least one corresponding reserved stride in a strided buffer; store each data packet in the at least one corresponding reserved stride; process the strided buffer upon storing the plurality of data packets in a corresponding plurality of reserved strides; and generate a completion notification indicating that the plurality of data packets in the strided buffer has been processed.
    Type: Application
    Filed: July 20, 2023
    Publication date: January 23, 2025
    Inventors: Ortal Ben Moshe, Roee Moyal, Shay Aisman, Gil Bloch, Ariel Shahar, Roman Nudelman, Gil Kremer, Yossef Itigin, Lior Narkis