Patents by Inventor Roee Moyal
Roee Moyal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12348410Abstract: Technologies for spreading packets of transport flows across multiple network paths are described. A network controller includes a transport layer and a network layer. The transport layer includes a flow scheduler to schedule a transport flow from one of a plurality of transport flows. The network layer includes multipath logic to receive packets from the transport flow and select which path of a plurality of paths to a destination to use for the packets based on path congestion weights corresponding to the plurality of paths.Type: GrantFiled: January 17, 2024Date of Patent: July 1, 2025Assignee: Mellanox Technologies, Ltd.Inventors: Yamin Friedman, Idan Borshteen, Roee Moyal, Yuval Shpigelman
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Patent number: 12323320Abstract: Technologies for spreading a burst of data across multiple network paths in remote direct memory access (RDMA) over converged Ethernet (RoCE) and InfiniBand are described. A network interface controller sends a first burst of a transport flow directed to a second node over a first network path. The network interface controller determines that a second burst is to be sent over a different network path, and identifies a second network path using a multipath context. The multipath context stores a first weight value or a first state associated with the first network path and a second weight value or a second state associated with the second network path. The network interface controller sends the second burst of data to the second node via the second network path.Type: GrantFiled: February 16, 2024Date of Patent: June 3, 2025Assignee: Mellanox Technologies, Ltd.Inventors: Yamin Friedman, Idan Borshteen, Roee Moyal, Yuval Shpigelman
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Patent number: 12316555Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry, and retrieve WRs from the multiple NSQs and execute data transmission operations specified in the WRs retrieved from the multiple NSQs.Type: GrantFiled: August 31, 2022Date of Patent: May 27, 2025Assignee: Mellanox Technologies, Ltd.Inventors: Gal Yefet, Daniel Marcovitch, Roee Moyal, Ariel Shahar, Gil Bloch, Lior Narkis
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Publication number: 20250165426Abstract: Devices, methods, and systems are provided. In one example, a device is described to include a device interface that receives data from at least one data source; a data shuffle unit that collects the data received from the at least one data source, receives a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, performs the data shuffle operation on the collected data to produce shuffled data, and provides the shuffled data to at least one data target.Type: ApplicationFiled: January 17, 2025Publication date: May 22, 2025Inventors: Daniel Marcovitch, Dotan David Levi, Eyal Srebro, Eliel Peretz, Roee Moyal, Richard Graham, Gil Bloch, Sean Pieper
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Patent number: 12229072Abstract: Devices, methods, and systems are provided. In one example, a device is described to include a device interface that receives data from at least one data source; a data shuffle unit that collects the data received from the at least one data source, receives a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, performs the data shuffle operation on the collected data to produce shuffled data, and provides the shuffled data to at least one data target.Type: GrantFiled: March 7, 2024Date of Patent: February 18, 2025Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Daniel Marcovitch, Dotan David Levi, Eyal Srebro, Eliel Peretz, Roee Moyal, Richard Graham, Gil Bloch, Sean Pieper
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Patent number: 12224950Abstract: In one embodiment, a system includes a memory to store a work queue including work queue entry slots, a processing device to write work queue entries to the work queue in a consecutive and cyclic manner, and a network device including a network interface to share packet over a network, and packet processing circuitry to read the work queue entries from the work queue in a consecutive and cyclic manner, the work queue entries indicating work to be performed associated with the packets, dequeue respective ones of the work queue entries read from the work queue responsively to reading the respective work queue entries from the work queue, add the work queue entries to an execution database used to track execution of the work queue entries, and execute the work queue entries in the execution database.Type: GrantFiled: November 2, 2022Date of Patent: February 11, 2025Assignee: Mellanox Technologies, LtdInventors: Gal Yefet, Daniel Marcovitch, Roee Moyal, Gil Bloch, Ariel Shahar, Yossef Itigin
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Publication number: 20250028658Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and a packet processing circuitry operatively coupled to the network interface. The packet processing circuitry may receive, via the network interface, a message; retrieve, via a packet processing circuitry, a work queue element (WQE) index identifying a position of a WQE in a receive queue; determine that the message is associated with a small payload; process the message without consuming the WQE; receive, via the network interface, a subsequent message; and process the subsequent message using the WQE. In this way, the systems and methods describe herein reduce the latency in processing of the data packets.Type: ApplicationFiled: July 20, 2023Publication date: January 23, 2025Inventors: Ortal Ben Moshe, Roee Moyal, Shay Aisman, Gil Bloch, Ariel Shahar, Roman Nudelman, Gil Kremer, Yossef Itigin, Lior Narkis
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Publication number: 20250030649Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and packet processing circuitry operatively coupled to the network interface. The packet processing circuitry is configured to receive, via the network interface, a plurality of data packets associated with a message; determine, for each data packet, at least one corresponding reserved stride in a strided buffer; store each data packet in the at least one corresponding reserved stride; process the strided buffer upon storing the plurality of data packets in a corresponding plurality of reserved strides; and generate a completion notification indicating that the plurality of data packets in the strided buffer has been processed.Type: ApplicationFiled: July 20, 2023Publication date: January 23, 2025Inventors: Ortal Ben Moshe, Roee Moyal, Shay Aisman, Gil Bloch, Ariel Shahar, Roman Nudelman, Gil Kremer, Yossef Itigin, Lior Narkis
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Publication number: 20250023829Abstract: An apparatus includes a memory and control circuitry. The control circuitry is configured to receive packets, which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order, to detect that one or more of the packets deviate from the sequential order, to buffer the one or more deviating packets in the memory, and, using the memory, to reorder the packets and provide the packets in the sequential order to the network device.Type: ApplicationFiled: October 1, 2024Publication date: January 16, 2025Inventors: Yamin Friedman, Idan Burstein, Ariel Shahar, Roee Moyal, Gil Kremer
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Publication number: 20250023668Abstract: In one embodiment, a first network device includes a host interface to receive messages from a host device, packet processing circuitry to send a batch of the messages to a second network device without waiting for an acknowledgement receipt from the second network device after sending each message, one message in the batch having a maximum message sequence number (MSN), receive a given acknowledgement receipt from the second network device indicating that all the messages in the batch have been received and including credit data indicating that there is no space in a receive work queue of the second network device for receiving an additional message, and send the additional message having an MSN greater than the maximum MSN to the second network device responsively to receiving the given acknowledgement receipt and based on the credit data indicating that there is no space in the receive work queue.Type: ApplicationFiled: July 13, 2023Publication date: January 16, 2025Inventors: Roee Moyal, Gil Kremer, Ortal Ben Moshe, Ariel Shahar
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Publication number: 20240411680Abstract: Apparatuses, systems, and techniques for dynamic memory allocation using a shared free list. A user tag is received, and a hashed user tag is generated. A first reference to an entry in a second data structure is identified in a first data structure using the hashed user tag. The entry includes multiple user tags. Responsive to determining that the multiple user tags do not include the user tag, a memory address is identified in a third data structure. The memory address is removed from the third data structure. Memory is allocated for a user context associated with the user tag at the memory address. The user tag is added to the second data structure.Type: ApplicationFiled: June 6, 2023Publication date: December 12, 2024Inventors: Gil Kremer, Roee Moyal, Igor Voks, Liel Peled, Eliel Peretz, Ariel Shahar
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Patent number: 12132665Abstract: An apparatus includes a memory and control circuitry. The control circuitry is configured to receive packets, which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order, to detect that one or more of the packets deviate from the sequential order, to buffer the one or more deviating packets in the memory, and, using the memory, to reorder the packets and provide the packets in the sequential order to the network device.Type: GrantFiled: November 21, 2022Date of Patent: October 29, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Yamin Friedman, Idan Burstein, Ariel Shahar, Roee Moyal, Gil Kremer
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Patent number: 12101239Abstract: A system includes a device coupled to a processing device. The processing device is to receive a request to execute a plurality of workloads, the request comprising a rate to execute each workload of the plurality of workloads and a parameter value indicating an execution offset. The processing device is further to determine a sequence for executing the plurality of workloads based on receiving the rate and the parameter value, where the sequence is to execute each workload at the respective rate and each workload of the plurality of workloads is executed at a different time based on the parameter value. The processing device is to execute the plurality of workloads in accordance with the sequence upon determining the sequence to execute the plurality of workloads.Type: GrantFiled: February 7, 2023Date of Patent: September 24, 2024Assignee: Mellanox Technologies, Ltd.Inventors: Natan Manevich, Dotan David Levi, Roee Moyal
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Publication number: 20240311184Abstract: A work descriptor identifying a plurality of workflow tasks to be performed by a hardware device is generated by a host system. The work descriptor corresponds to a performance completion message generated by the hardware device in response to completing performance of the work descriptor. One or more completion indicators are added to the work descriptor. Each of the completion indicators instructs the hardware device to generate one or more additional completion messages during performance of the work descriptor in response to a trigger criterion. The work descriptor is caused to be available to the hardware device for execution.Type: ApplicationFiled: October 26, 2023Publication date: September 19, 2024Inventors: Natan Manevich, Wojciech Wasko, Dotan David Levi, Ariel Shahar, Roee Moyal, Eliel Peretz
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Publication number: 20240311183Abstract: A work descriptor identifying a plurality of workflow tasks to be performed by a hardware device is generated by a host system. A plurality of timestamp logging tasks are added to the work descriptor. Each of the plurality of timestamp logging tasks corresponds to one of the plurality of workflow tasks and instructs the hardware device to log a timestamp in response to an event associated with a respective workflow task. The work descriptor with the plurality of timestamp logging tasks is stored in a work queue of the host system. The work queue is accessible by the hardware device.Type: ApplicationFiled: October 2, 2023Publication date: September 19, 2024Inventors: Natan Manevich, Ariel Shahar, Wojciech Wasko, Dotan David Levi, Roee Moyal, Eliel Peretz
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Patent number: 12047478Abstract: A system including a network interface layer, and a physical network connection configured to connect with a networking medium. The network interface layer is configured to: A) receive a plurality of user datagram protocol (UDP) message segments from the physical network connection; B) coalesce the plurality of UDP message segments into a coalesced UDP message; and C) send the coalesced UDP message to an application layer external to the system. Related apparatus and methods are also provided.Type: GrantFiled: January 27, 2021Date of Patent: July 23, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Boris Pismenny, Liran Liss, Yossi Kuperman, Roee Moyal
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Publication number: 20240211426Abstract: Devices, methods, and systems are provided. In one example, a device is described to include a device interface that receives data from at least one data source; a data shuffle unit that collects the data received from the at least one data source, receives a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, performs the data shuffle operation on the collected data to produce shuffled data, and provides the shuffled data to at least one data target.Type: ApplicationFiled: March 7, 2024Publication date: June 27, 2024Inventors: Daniel Marcovitch, Dotan David Levi, Eyal Srebro, Eliel Peretz, Roee Moyal, Richard Graham, Gil Bloch, Sean Pieper
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Publication number: 20240195728Abstract: Technologies for spreading a burst of data across multiple network paths in remote direct memory access (RDMA) over converged Ethernet (RoCE) and InfiniBand are described. A network interface controller sends a first burst of a transport flow directed to a second node over a first network path. The network interface controller determines that a second burst is to be sent over a different network path, and identifies a second network path using a multipath context. The multipath context stores a first weight value or a first state associated with the first network path and a second weight value or a second state associated with the second network path. The network interface controller sends the second burst of data to the second node via the second network path.Type: ApplicationFiled: February 16, 2024Publication date: June 13, 2024Inventors: Yamin Friedman, Idan Borshteen, Roee Moyal, Yuval Shpigelman
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Publication number: 20240187336Abstract: Technologies for spreading packets of transport flows across multiple network paths are described. A network controller includes a transport layer and a network layer. The transport layer includes a flow scheduler to schedule a transport flow from one of a plurality of transport flows. The network layer includes multipath logic to receive packets from the transport flow and select which path of a plurality of paths to a destination to use for the packets based on path congestion weights corresponding to the plurality of paths.Type: ApplicationFiled: January 17, 2024Publication date: June 6, 2024Inventors: Yamin Friedman, Idan Borshteen, Roee Moyal, Yuval Shpigelman
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Publication number: 20240171520Abstract: An apparatus includes a memory and control circuitry. The control circuitry is configured to receive packets, which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order, to detect that one or more of the packets deviate from the sequential order, to buffer the one or more deviating packets in the memory, and, using the memory, to reorder the packets and provide the packets in the sequential order to the network device.Type: ApplicationFiled: November 21, 2022Publication date: May 23, 2024Inventors: Yamin Friedman, Idan Burstein, Ariel Shahar, Roee Moyal, Gil Kremer