Abstract: A method (100) is disclosed of generating an identifier from a semiconductor device (600) comprising a volatile memory (610) having a plurality of memory cells. The method comprises causing (110) the memory cells to assume a plurality of pseudo-random bit values inherent to variations in the microstructure of the memory cells; retrieving (120) the bit values from at least a subset of the plurality of memory cells; and generating the identifier from the retrieved bit values. The method (100) is based on the realization that a substantial amount of the cells of a volatile memory can assume a bit value that is governed by underlying variations in manufacturing process parameters; this for instance occurs at power-up for an SRAM or after a time period without refresh for a DRAM.

Abstract: A method (100) is disclosed of generating an identifier from a semiconductor device (600) comprising a volatile memory (610) having a plurality of memory cells. The method comprises causing (110) the memory cells to assume a plurality of pseudo-random bit values inherent to variations in the microstructure of the memory cells; retrieving (120) the bit values from at least a subset of the plurality of memory cells; and generating the identifier from the retrieved bit values. The method (100) is based on the realization that a substantial amount of the cells of a volatile memory can assume a bit value that is governed by underlying variations in manufacturing process parameters; this for instance occurs at power-up for an SRAM or after a time period without refresh for a DRAM.

Abstract: An IC is provided with supply pins extending beyond the chip's encapsulation. The location of the supply pins is chosen so as to minimize the length of the associated bonding wires. Moreover the supply pins are located next to each other so as to reduce the effective inductance of the associated bonding wires. Output pins connected with on-chip buffers are located next to the supply pins so as to reduce the length of the buffer's supply lines, giving rise to a further reduction is inductive parasitic effects.

Abstract: An integrated memory circuit in which memory cells are arranged in rows and columns, each column having a separate sense amplifier. The memory columns can be coupled to neighboring memory columns by additional transistors and the gain of the sense amplifiers in the even and the odd columns is adjustable. Consequently, information can also be serially shifted from one column to another, so that the information can be written and read not only in parallel but also serially.

Abstract: The invention relates to an additional transistor which is connected in cascode with a sub-circuit of a logic circuit in order to protect further transistors of the sub-circuit against hot carrier stress and hot carrier degradation. In a logic circuit having transistors of a first conductivity type, an additional transistor of the second conductivity type is arranged in cascode. This additional transistor is connected as a diode or as a current source in dependence on an output voltage of the circuit. Further aspects of the invention concern the switching means for switching the additional transistor and the location where the additional transistor is to be inserted.

Abstract: A random access memory (1) is described in which one address of a row of addresses is activatable. There is also realized a block addressing mode in which all addresses between a selectable first address and a selectable second address are activated. To this end there are provided two address registers (4, 5) and a logic tree structure (8) which consists of modules. At each level of the tree structure a module receives a part of the information from the two address registers in order to determine, possibly co-controlled by information received from a higher level of the tree, whether one or both limit addresses are situated within the address range covered by the module and, if the answer is negative, to determine whether all addresses of this address range must be activated or remain deactivated.

Abstract: An integrated logic circuit includes an output circuit for generating an output current which increases linearly in time. In integrated logic circuits the problem presents itself that the rapid variation of the (dis) charging of a data output causes a reverse voltage pulse VL across the inductance formed by the connection wires. The reverse voltage is limited by causing the charge or discharge current (for the load capacities present) to increase linearly to a maximum permissible value. This is done by driving the output field effect transistor with a control voltage VC which varies in time in the form of a square root.

Abstract: A high packing density is obtained in a memory by stacking the capacitors of adjacent columns in such a manner that two capacitors of different columns are formed by three conductive layers situated one above the other. The central layer can be connected to a reference voltage, while the uppermost layer is connected to a transistor in one column and lowermost layer is connected to a transistor in the other column.

Abstract: In a memory cell array of the kind including a memory cell capacitor and a memory cell transistor connected in series between a field plate line and a bit line, both the field plate line and bit line are precharged to the same potential level. The field plate line is connected to one input of a sense amplifier and the bit line is connected to the other input. The charge and discharge of the memory cell capacitor causes equal and opposite voltage changes on the field plate line and bit line. With respect to prior art the cell signal is increased by the amount of signal on the field plate line and when sensed against a reference signal which is about one-half the amount of the cell signal, the sensed signal is about twice that obtainable in the prior art.

Abstract: An integrated circuit in dynamic MOS logic is composed of combinatory and sequential logic elements. Each of the latter comprises a succession of an input gate, an intermediate gate and an output gate which are activated to conduct by a corresponding phase of the first one and subsequent phases of a clock pulse cycle. The combinatory logic elements are all composed of gates of a single type, while the input signals are applied via the sequential logic elements and the output signals are output again via the latter elements. Thus, in the combinatory network only a sole type of interference is still relevant.

Abstract: A method of fabricating a double polysilicon MOS structure of reduced size employs local oxidation of polysilicon to define and isolate a first polysilicon layer. Prior to etching the first polysilicon layer, a first masking step defines one of the elements of the MOS transistor, such as the source. By selectively etching the first polysilicon layer, the isolation regions and then the other elements of the MOS transistor are defined. With only slight variations in the simplified process, either a plurality of one MOS transistor-one capacitor memory cells or a plurality of MOS transistors can be fabricated.

Abstract: A simple MOS voltage divider uses three enhancement MOS transistors, which includes one load connected to two drivers in parallel. The gate of one driver is connected to the output node, and the other two gates are connected to the supply voltage. The transistors have a common substrate.By proper choice of the transistor geometry only, the output node voltage can be made independent of the threshold and temperature variations for output voltages larger than one threshold and smaller than one-half the supply voltage. Moreover, the ratio between the output and supply voltages remains constant.

Abstract: A word-organized, content-addressable memory comprises per word location a validity indicator, having a position "valid" and a position "invalid", and a correspondence indicator. The following functions can be performed:(a) associative searching and reading of the content of a word for which correspondence occurs (R);(b) reading the next word in sequence of words for which correspondence occurs (SR);(c) loading a mask word in the mask register (LM);(d) selective invalidating of the content of one or more predetermined word locations (CPM);(e) writing in an empty word location, i.e. a location not having a valid data content (WFP);(f) writing data in a number of selective bit positions of one or more words for which correspondence occurs (WP).There is also provided a mask register whose data activate the comparisons as well as the outputting of data for which no comparison has taken place.As a result of such an organization, a very versatile use is realized for a comparatively inexpensive memory.

Abstract: A semiconductor device having an integrated circuit of which a region of one conductivity type is charged by supplying charge carriers from a zone of the opposite conductivity type to an inversion layer formed in the said region below a field electrode at which a voltage is set up. When the voltage is switched off, a part of the charge carriers recombine in the said region. According to the invention, the charge carriers are supplied from a supply conductor and an electronic switch is present between said conductor and the inversion layer, which switch prevents the flow back of charge carriers to the supply conductor when the inversion layer disappears.

Abstract: The invention relates to a JFET memory in which the information at the gate electrodes of the JFET's is stored and read-out non-destructively. Each JFET has an IGFET structure situated entirely within the JFET and the gate of which is coupled to the source or drain of the JFET. The information can be refreshed periodically at cell level (that is without external amplifiers) by means of said IGFET.

Abstract: A random access memory (RAM) in which each memory cell includes a JFET having two gate electrodes selectable by means of a single word line and a single bit line. The JFETs have a common electrode formed from the substrate of a semiconductor body common to each of the memory cells, which serves as one of the main electrodes of each of the JFETs.

Abstract: JFET memory structures, in particular for RAM's with non-destructive reading-out of the charge state of a floating gate electrode in which the primary selection is realized by means of capacitive coupling with the floating gate electrode. The secondary selection takes place on one of the main electrodes of the JFET structures in which the other main electrode can be connected to the supply. By means of a second common gate electrode the pinch-off voltage of the channels can be adjusted so that the channels are non-conductive in the non-selected condition and a good detection of the information state is obtained in the selected condition.