Patents by Inventor Roger A. Bethard
Roger A. Bethard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8126674Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.Type: GrantFiled: August 27, 2010Date of Patent: February 28, 2012Assignee: Cray Inc.Inventors: David R. Resnick, Gerald A. Schwoerer, Kelly J. Marquardt, Alan M. Grossmeier, Michael L. Steinberger, Van L. Snyder, Roger A. Bethard
-
Patent number: 8051338Abstract: An apparatus includes a SerDes circuit and a link control block (LCB). The SerDes circuit is a first end of a SerDes circuit pair of a SerDes lane. A SerDes lane includes the SerDes circuit pair coupled by a communications medium. The LCB includes an error tracking circuit and a controller. The controller includes an error recovery module configured to retry a data communication when an error is detected and deactivate the SerDes lane when a rate of errors on the SerDes lane exceeds a threshold error rate value. Other devices, systems, and methods are disclosed.Type: GrantFiled: July 19, 2007Date of Patent: November 1, 2011Assignee: Cray Inc.Inventor: Roger A. Bethard
-
Publication number: 20110150136Abstract: A data communication receiver includes an interface operable to receive at least one incoming data signal. A transition point tracker is operable to track data transition points of the data signal, and a data sampler is operable to sample the data signal at a desired sampling point between transition points.Type: ApplicationFiled: December 21, 2009Publication date: June 23, 2011Applicant: Cray Inc.Inventor: Roger A. Bethard
-
Patent number: 7890673Abstract: A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs, and/or a block transfer engine (BTE) that optionally includes a serial cabinet-to-cabinet communications path (MLINK). In some embodiments, the processor TLBs are located within one or more common memory sections, each memory section being connected to a plurality of processors, wherein each processor TLB is associated with one of the processors. The BTE performs efficient memory-to-memory data transfers without further processor intervention. The MLINK extends the BTE functionality beyond a single cabinet.Type: GrantFiled: December 14, 2006Date of Patent: February 15, 2011Assignee: Cray Inc.Inventor: Roger A. Bethard
-
Publication number: 20100324854Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.Type: ApplicationFiled: August 27, 2010Publication date: December 23, 2010Applicant: CRAY INC.Inventors: David R. Resnick, Gerald A. Schwoerer, Kelly J. Marquardt, Alan M. Grossmeier, Michael L. Steinberger, Van L. Snyder, Roger A. Bethard
-
Patent number: 7830905Abstract: A system and method for speculative forwarding of packets received by a router, wherein each packet includes phits and wherein one or more phits include a cyclic redundancy code (CRC). A packet is received and phits of the packet are forwarded to router logic. A cyclic redundancy code for the packet is calculated and compared to the packet's cyclic redundancy code. An error is generated if the cyclic redundancy codes don't match. If the cyclic redundancy codes don't match, a phit of the packet is modified to reflect the error, the CRC is corrected and the corrected CRC is forwarded to the router logic along with the phit reflecting the CRC error. At the router logic, a check is made to see if the packet is still within the router logic. If the packet is still within the router logic and there was a CRC error, the packet is discarded. If, however, the packet is no longer within the router logic and there was a CRC error, the packet is modified so that the next router discards the packet.Type: GrantFiled: April 21, 2008Date of Patent: November 9, 2010Assignee: Cray Inc.Inventors: Steven L. Scott, Gregory Hubbard, Kelly Marquardt, Roger A. Bethard, Dennis C. Abts
-
Patent number: 7826996Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.Type: GrantFiled: February 26, 2007Date of Patent: November 2, 2010Assignee: Cray Inc.Inventors: David R. Resnick, Gerald A. Schwoerer, Kelly J. Marquardt, Alan M. Grossmeier, Michael L. Steinberger, Van L. Snyder, Roger A. Bethard
-
Publication number: 20090028172Abstract: A system and method for speculative forwarding of packets received by a router, wherein each packet includes phits and wherein one or more phits include a cyclic redundancy code (CRC). A packet is received and phits of the packet are forwarded to router logic. A cyclic redundancy code for the packet is calculated and compared to the packet's cyclic redundancy code. An error is generated if the cyclic redundancy codes don't match. If the cyclic redundancy codes don't match, a phit of the packet is modified to reflect the error, the CRC is corrected and the corrected CRC is forwarded to the router logic along with the phit reflecting the CRC error. At the router logic, a check is made to see if the packet is still within the router logic. If the packet is still within the router logic and there was a CRC error, the packet is discarded. If, however, the packet is no longer within the router logic and there was a CRC error, the packet is modified so that the next router discards the packet.Type: ApplicationFiled: April 21, 2008Publication date: January 29, 2009Applicant: Cray Inc.Inventors: Steven L. Scott, Gregory Hubbard, Kelly Marquardt, Roger A. Bethard, Dennis C. Abts
-
Publication number: 20090024883Abstract: An apparatus comprising a SerDes circuit and a link control block (LCB). The SerDes circuit is a first end of a SerDes circuit pair of a SerDes lane. A SerDes lane includes the SerDes circuit pair coupled by a communications medium. The LCB includes an error tracking circuit and a controller. The controller includes an error recovery module configured to retry a data communication when an error is detected and deactivate the SerDes lane when a rate of errors on the SerDes lane exceeds a threshold error rate value. Other devices, systems, and methods are disclosed.Type: ApplicationFiled: July 19, 2007Publication date: January 22, 2009Inventor: Roger A. Bethard
-
Publication number: 20080059105Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.Type: ApplicationFiled: February 26, 2007Publication date: March 6, 2008Applicant: CRAY INC.Inventors: David Resnick, Gerald Schwoerer, Kelly Marquardt, Alan Grossmeier, Michael Steinberger, Van Snyder, Roger Bethard
-
Patent number: 7320100Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.Type: GrantFiled: May 19, 2004Date of Patent: January 15, 2008Assignee: Cray Inc.Inventors: R. Paul Dixon, David R. Resnick, Gerald A. Schwoerer, Kelly J. Marquardt, Alan M. Grossmeier, Michael L. Steinberger, Van L. Snyder, Roger A. Bethard, Michael F. Higgins
-
Publication number: 20070088932Abstract: A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs, and/or a block transfer engine (BTE) that optionally includes a serial cabinet-to-cabinet communications path (MLINK). In some embodiments, the processor TLBs are located within one or more common memory sections, each memory section being connected to a plurality of processors, wherein each processor TLB is associated with one of the processors. The BTE performs efficient memory-to-memory data transfers without further processor intervention. The MLINK extends the BTE functionality beyond a single cabinet.Type: ApplicationFiled: December 14, 2006Publication date: April 19, 2007Inventor: Roger Bethard
-
Patent number: 7184916Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.Type: GrantFiled: May 19, 2004Date of Patent: February 27, 2007Assignee: Cray Inc.Inventors: David R. Resnick, Gerald A. Schwoerer, Kelly J. Marquardt, Alan M. Grossmeier, Michael L. Steinberger, Van L. Snyder, Roger A. Bethard
-
Patent number: 7162608Abstract: A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs, and/or a block transfer engine (BTE) that optionally includes a serial cabinet-to-cabinet communications path (MLINK). In some embodiments, the processor TLBs are located within one or more common memory sections, each memory section being connected to a plurality of processors, wherein each processor TLB is associated with one of the processors. The BTE performs efficient memory-to-memory data transfers without further processor intervention. The MLINK extends the BTE functionality beyond a single cabinet.Type: GrantFiled: October 24, 2001Date of Patent: January 9, 2007Assignee: Cray, Inc.Inventor: Roger A. Bethard
-
Publication number: 20050022065Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.Type: ApplicationFiled: May 19, 2004Publication date: January 27, 2005Inventors: R. Dixon, David Resnick, Gerald Schwoerer, Kelly Marquardt, Alan Grossmeier, Michael Steinberger, Van Snyder, Roger Bethard, Michael Higgins
-
Publication number: 20040267481Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.Type: ApplicationFiled: May 19, 2004Publication date: December 30, 2004Inventors: David R. Resnick, Gerald A. Schwoerer, Kelly J. Marquardt, Alan M. Grossmeier, Michael L. Steinberger, Van L. Snyder, Roger A. Bethard
-
Publication number: 20030079104Abstract: A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs, and/or a block transfer engine (BTE) that optionally includes a serial cabinet-to-cabinet communications path (MLINK). In some embodiments, the processor TLBs are located within one or more common memory sections, each memory section being connected to a plurality of processors, wherein each processor TLB is associated with one of the processors. The BTE performs efficient memory-to-memory data transfers without further processor intervention. The MLINK extends the BTE functionality beyond a single cabinet.Type: ApplicationFiled: October 24, 2001Publication date: April 24, 2003Inventor: Roger A. Bethard
-
Patent number: 6496544Abstract: An adaptive computing system having trainable components for eliminating harmful effects of skew caused by the length of the transmission line or introduced by data-dependent sources. A transmitter provides a data value to the transmission line according to an output clock signal and precompensates the transmission line when a change in the data value is detected. A receiver is communicatively coupled to the transmitter by the transmission line and has a plurality of data latches. Each data latch stores a data value received from the transmission line according to a unique clock signal. All configuration and training of the adaptive transmitter and receiver is accomplished through a standard boundary scan register that complies with IEEE/ANSI standard 1149.1-1990.Type: GrantFiled: December 14, 1998Date of Patent: December 17, 2002Assignee: Cray Inc.Inventor: Roger A. Bethard