Abstract: A sloped roof vent has a coated steel plate with a raised center and a gasket receiver is formed around a central hole. A structural body is crimped with a gasket in the receiver. The body has an outer wall extending downward over the receiver. A sloping wall extends inward and a vertical wall supports a second sloping wall with an inner rim. A damper staked to an axle covers the rim. Inserts keep the damper from chattering and fully closing. Wind walls prevent outer drafts from lifting the damper. Two fasteners attach caps to the outer wall. Lanced and pressed ledges on a push-in hose connector permanently engage windows on the inner rim of the structural body. A snap-in screen and a hose connector reducer complete a package.

Abstract: A sloped roof vent has a coated steel plate with a raised center and a gasket receiver is formed around a central hole. A structural body is crimped with a gasket in the receiver. The body has an outer wall extending downward over the receiver. A sloping wall extends inward and a vertical wall supports a second sloping wall with an inner rim. A damper staked to an axle covers the rim. Inserts keep the damper from chattering and fully closing. Wind walls prevent outer drafts from lifting the damper. Two fasteners attach caps to the outer wall. Lanced and pressed ledges on a push-in hose connector permanently engage windows on the inner rim of the structural body. A snap-in screen and a hose connector reducer complete a package.

Abstract: A sloped roof vent has a coated steel plate with a raised center and a gasket receiver is formed around a central hole. A structural body is crimped with a gasket in the receiver. The body has an outer wall extending downward over the receiver. A sloping wall extends inward and a vertical wall supports a second sloping wall with an inner rim. A damper staked to an axle covers the rim. Inserts keep the damper from chattering and fully closing. Wind walls prevent outer drafts from lifting the damper. Two fasteners attach caps to the outer wall. Lanced and pressed ledges on a push-in hose connector permanently engage windows on the inner rim of the structural body. A snap-in screen and a hose connector reducer complete a package.

Abstract: A circuit for protecting against electrostatic discharge events has a semiconductor substrate (200) of first conductivity embedding a first diode in a well (260) of opposite second conductivity, the diode's anode (111) tied to an I/O pin-to-be-protected (101) at a first voltage, and the first diode's cathode (112) connected to the first drain (123) of a first MOS transistor in the substrate. The first MOS transistor's first gate (122) is biased to a second voltage smaller than the first voltage, thereby reducing the first voltage by the amount of the second voltage. In series with the first MOS transistor is a second MOS transistor with its second drain (670) merged with the first source of the first MOS transistor, and its second source (131), together with its second gate (132), tied to ground potential (140).

Abstract: A circuit for protecting against electrostatic discharge events has a semiconductor substrate (200) of first conductivity embedding a first diode in a well (260) of opposite second conductivity, the diode's anode (111) tied to an I/O pin-to-be-protected (101) at a first voltage, and the first diode's cathode (112) connected to the first drain (123) of a first MOS transistor in the substrate. The first MOS transistor's first gate (122) is biased to a second voltage smaller than the first voltage, thereby reducing the first voltage by the amount of the second voltage. In series with the first MOS transistor is a second MOS transistor with its second drain (670) merged with the first source of the first MOS transistor, and its second source (131), together with its second gate (132), tied to ground potential (140).

Abstract: A circuit for protecting against electrostatic discharge events has a semiconductor substrate (200) of first conductivity embedding a first diode in a well (260) of opposite second conductivity, the diode's anode (111) tied to an I/O pin-to-be-protected (101) at a first voltage, and the first diode's cathode (112) connected to the first drain (123) of a first MOS transistor in the substrate. The first MOS transistor's first gate (122) is biased to a second voltage smaller than the first voltage, thereby reducing the first voltage by the amount of the second voltage. In series with the first MOS transistor is a second MOS transistor with its second drain (670) merged with the first source of the first MOS transistor, and its second source (131), together with its second gate (132), tied to ground potential (140).

Abstract: A circuit for protecting against electrostatic discharge events has a semiconductor substrate (200) of first conductivity embedding a first diode in a well (260) of opposite second conductivity, the diode's anode (111) tied to an I/O pin-to-be-protected (101) at a first voltage, and the first diode's cathode (112) connected to the first drain (123) of a first MOS transistor in the substrate. The first MOS transistor's first gate (122) is biased to a second voltage smaller than the first voltage, thereby reducing the first voltage by the amount of the second voltage. In series with the first MOS transistor is a second MOS transistor with its second drain (670) merged with the first source of the first MOS transistor, and its second source (131), together with its second gate (132), tied to ground potential (140).

Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.

Abstract: A system and method are provided for simple yet reliable replacement and sealing of existing vent pipe penetrations through an external surface of a structure such as a building's roof. The system and method replace a portion of an existing vent pipe with a sealed replacement pipe extension. The replacement pipe extension and remaining portion of the existing vent pipe are preferably combined with a pipe flashing structure to provide a sealed replacement pipe solution capable of withstanding torsional and side loads encountered in rooftop applications. The system and method enable replacement and sealing tasks quickly and at low cost.

Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.

Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.

Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.

Abstract: An electrostatic protection circuit has a transistor for pumping charge into the substrate and a transistor, including a parasitic transistor, for removing charge from the substrate and tabs. The circuit is enclosed by barrier that prevents the migration of charge from the region of the transistors. The added charge in the region of the parasitic transistor, resulting from the increased charge in the region of the parasitic transistor, increases the flow of current between electrodes of the transistor, thereby removing the electrostatic charge more efficiently. removing the electrostatic charge more efficiently.

Abstract: The voltage tolerant circuit with improved latchup suppression includes: a diode device having a first end coupled to a source voltage node; a first NWELL guard ring surrounding the diode device; a diode coupled between a second end of the string of diodes and an output pad; a second NWELL guard ring surrounding the diode; and a transistor device coupled between the output pad and a substrate node. The NWELL guardrings disrupt the parasitic SCR operation by adding an additional N+ diffusion without affecting the substrate pump current delivered by the diode.

Abstract: Protection circuitry (100) for protecting an integrated circuit against an ESD pulse is provided. The protection circuitry (100) includes a discharge circuitry (101) on a substrate (106) that discharges an ESD pulse to the integrated circuit to ground (104a). The protection circuitry (100) also includes a drive circuitry (102) that uses a portion of the ESD pulse voltage to bias the substrate (106) using a first guard ring (110) in the substrate (106), which surrounds the discharge circuitry (101) and drive circuitry (102). The protection circuitry (100) further includes a second guard ring (120) in substrate (106), which surrounds the first guard ring (110) and connects to Vss/ground potential (104c), thereby providing uniformity of the substrate bias.

Abstract: The voltage tolerant circuit with improved latchup suppression includes: a diode device having a first end coupled to a source voltage node; a first NWELL guard ring surrounding the diode device; a diode coupled between a second end of the string of diodes and an output pad; a second NWELL guard ring surrounding the diode; and a transistor device coupled between the output pad and a substrate node. The NWELL guardrings disrupt the parasitic SCR operation by adding an additional N+ diffusion without affecting the substrate pump current delivered by the diode.

Abstract: An output circuit for improved ESD protection (FIG. 2) comprising a pMOS pull-up output transistor connected between a signal (I/O) pad 220 and Vdd power supply 240, the pull-up transistor located in a n-well 203 and having at least one gate 210, the gate connected to internal circuitry 230. A dummy pMOS transistor connected in parallel with the pull-up transistor, the dummy transistor also located in the n-well 203, whereby both the pull-up transistor and the dummy transistor participate in protection against an ESD event. The dummy transistor having at least one gate 251, this gate connected through a resistor 260 to the Vdd power supply 240. The n-well 203 connected to the Vdd power supply 240.

Abstract: Protection circuitry (100) for protecting an integrated circuit against an ESD pulse is provided. The protection circuitry (100) includes a discharge circuitry (101) on a substrate (106) that discharges an ESD pulse to the integrated circuit to ground (104a). The protection circuitry (100) also includes a drive circuitry (102) that uses a portion of the ESD pulse voltage to bias the substrate (106) using a first guard ring (110) in the substrate (106), which surrounds the discharge circuitry (101) and drive circuitry (102). The protection circuitry (100) further includes a second guard ring (120) in substrate (106), which surrounds the first guard ring (110) and connects to Vss/ground potential (104c), thereby providing uniformity of the substrate bias.

Abstract: An integrated circuit is provided with a local electrostatic discharge (ESD) protection circuitry (120) associated with each signal pad. The integrated circuit has internal circuitry (100) that operates at a low supply voltage, but at least some of the interface signals impressed on the signal pads operate at a high supply voltage. The local ESD protection circuitry associated with each signal pad comprises only a pair of diodes connected respectively to the ground reference bus and a high voltage supply bus. A few shared clamp circuits (222) are connected to the voltage buses and clamp any ESD voltage surge that is transferred to the high voltage bus by the individual signal pad ESD protection circuits. The clamp circuits use cascoded low voltage MOS devices (P1, N1, P2) that are biased during normal operation so that electrical over-stress does not occur.