Abstract: A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented) with each clock. To prevent the watchdog timer circuit from becoming triggered, the watchdog timer circuit should be reset or reloaded by software. For example, the count register may be reset to a value to start the count over. If the count register is allowed to count to a final or maximum value, the watchdog timer circuit will become triggered, generating a triggered signal that causes the programmable logic integrated circuit to be reset. A reset causes a reloading of the configuration data used to program the programmable logic and embedded processor portions of the integrated data. The configuration data may be stored in an external nonvolatile storage memory.

Abstract: A method and apparatus for configuring a digital system having a programmable logic device and embedded logic from a configuration source that supplies a single serialized configuration bit stream for configuring both the programmable logic device and the embedded logic.

Abstract: A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented) with each clock. To prevent the watchdog timer circuit from becoming triggered, the watchdog timer circuit should be reset or reloaded by software. For example, the count register may be reset to a value to start the count over. If the count register is allowed to count to a final or maximum value, the watchdog timer circuit will become triggered, generating a triggered signal that causes the programmable logic integrated circuit to be reset. A reset causes a reloading of the configuration data used to program the programmable logic and embedded processor portions of the integrated data. The configuration data may be stored in an external nonvolatile storage memory.

Abstract: The present invention provides an effective method of inhibiting corrosion on metallic surfaces in contact with a fluid contained in a closed loop industrial fluid system, which comprises adding to such fluid an effective corrosion controlling amount of a combination of an organic diacid, a triamine and a phosphonate compound.

Abstract: Methods for reducing calcium deposition along surfaces in contact with the water phase of a resolved water/oil emulsion are disclosed. High calcium crude oil and the like are contacted with a sequestrant to form a sequestered calcium containing complex that partitions to the water phase in the resolved emulsion. A specifically formulated polymeric deposit control agent is added to the water phase to inhibit calcium deposit formation therein and along surfaces in contact with the water phase.

Abstract: The present invention provides circuitry and methods for sharing I/O pins between a programmable logic portion and an embedded processor portion of a chip. The circuits in the programmable logic portion and the embedded processor portion can access data signals from and send data signals to the same I/O pins. The data signals are multiplexed to control access to the shared I/O pins. The multiplexers may be controlled by a control signal that determines when particular I/O pins are accessed by the programmable logic portion and the embedded processor portion. Control signals that configure the associated I/O pin circuitry to the correct I/O standard are also multiplexed by the shared I/O circuitry of the present invention. Signals received at the shared I/O pins that are transmitted to the embedded processor portion may be concurrently sent to snoop circuitry within the programmable logic portion.

Abstract: Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port.

Abstract: A programmable logic device is reconfigurable between two functionalities, while it is in use. The programmable logic device has a first store, into which configuration data may be downloaded from an external memory device, and a second store, in which a copy of the configuration data is maintained, with the functionality of the programmable logic device being determined by the copy of the configuration data, thereby allowing additional configuration data to be downloaded from the external memory device into the first store, while maintaining the functionality of the device. This allows the device to be used to provide two different functionalities, and to be switched between these two functionalities with minimal delay for reconfiguration of the device.

Abstract: A programmable logic device includes a routing structure, which takes the form of multiple distributed OR gates, which are positioned within the device to allow signals to be input from spaced apart logic elements, and present the input signals to other logic elements, which, again, may be spaced apart throughout the device. Each of the distributed OR gates, and its connections to the other logic elements, acts as a multiplexer. Sufficient of these distributed OR gates are provided to allow a bus structure to be implemented within the device. Since the OR gates are provided separately from the logic elements of the programmable logic device, the required bus structure can be implemented more efficiently.

Abstract: A programmable logic device is provided with multiple power supplies such that, in one mode of operation, power can be disconnected from at least one part of the programmable logic device, while maintaining power at least to an interface component of the programmable logic device, or to a memory component in which current configuration data are stored, thereby avoiding the need for a configuration sequence when power is reapplied to the whole device. The programmable logic device may be provided as an integrated circuit, having multiple pairs of pins for connection to a supply voltage. Each of the pairs of pins provides power for a different subsection of the programmable logic device.

Abstract: The present invention provides circuitry and methods for sharing I/O pins between a programmable logic portion and an embedded processor portion of a chip. The circuits in the programmable logic portion and the embedded processor portion can access data signals from and send data signals to the same I/O pins. The data signals are multiplexed to control access to the shared I/O pins. The multiplexers may be controlled by a control signal that determines when particular I/O pins are accessed by the programmable logic portion and the embedded processor portion. Control signals that configure the associated I/O pin circuitry to the correct I/O standard are also multiplexed by the shared I/O circuitry of the present invention. Signals received at the shared I/O pins that are transmitted to the embedded processor portion may be concurrently sent to snoop circuitry within the programmable logic portion.

Abstract: A programmable logic device includes a gate array formed from programmable logic elements, and at least one address decoder structure. The address decoder has a first stage, for receiving bits of an address, and for masking out a first group of least significant bits of said address; a second stage, for comparing a second group of most significant bits of said address with respective comparison bits; and a third stage, for providing an output when all of the bits in said second group of bits of said address match their respective comparison bits. Thus, the address decoder can determine when a received address falls within a range of addresses associated with the address decoder. Multiple address decoders may be provided at spaced apart locations within the gate array, and one address decoder can be associated with each slave device implemented in the gate array. The programmable logic device may be used to implement a bus structure, with a bus master which may be in the form of an embedded processor.

Abstract: A multiple bus architecture for a system on a chip including bridges for de-coupling clock frequencies of individual bus masters from peripherals they are accessing. Each bridge interfaces to all bus masters in the system that require access to the peripherals it interfaces to.

Abstract: The present invention provides circuitry and methods for sharing I/O pins between a programmable logic portion and an embedded processor portion of a chip. The circuits in the programmable logic portion and the embedded processor portion can access data signals from and send data signals to the same I/O pins. The data signals are multiplexed to control access to the shared I/O pins. The multiplexers may be controlled by a control signal that determines when particular I/O pins are accessed by the programmable logic portion and the embedded processor portion. Control signals that configure the associated I/O pin circuitry to the correct I/O standard are also multiplexed by the shared I/O circuitry of the present invention. Signals received at the shared I/O pins that are transmitted to the embedded processor portion may be concurrently sent to snoop circuitry within the programmable logic portion.

Abstract: A multiple bus architecture for a system on a chip including bridges for decoupling clock frequencies of individual bus masters from peripherals they are accessing. Each bridge interfaces to all bus masters in the system that require access to the peripherals it interfaces to.

Abstract: A method and apparatus for configuring a digital system having a programmable logic device and embedded logic from a configuration source that supplies a single serialized configuration bit stream for configuring both the programmable logic device and the embedded logic.

Abstract: This technique involves digitally filtering data by determining the median of data values instead of mean or some other algebraic combination. It is unique in that the data used for the median calculation utilizes previous as well as the new data. This filter structure can be used in both time domain and spatial domain. Also, the filter size can easily be varied to permit adapting its size to system gain.

Abstract: A window generator is disclosed which provides a unique 6 bit target identification number for up to 63 target areas and one background area in a frame of serially scanned data. Any number of target areas can be identified by increasing memory width. The target numbers allow video pipeline processing circuitry to collect statistics separately for each target area. A target number is provided for each pixel as the image is scanned in a raster can format. The target areas are defined as rectangular sectors with background at all other non-target locations. The window generator has contained in a RAM the data necessary to define the window areas. This data is calculated and formatted off-line by a microprocessor and downloaded into the RAM. Information contained in the RAM represents the number of pixels between any two successive target area corners along with a two bit command word.

Abstract: Noise smoothing of imaging data is performed using frame integration, by averaging pixels over time instead of space, without resulting in a smear of moving objects by: sensing image motion; and enabling frame integration on only stationary scene pixels. Image motion is sensed by: producing a differencing signal which indicates the difference between new image data and frame integrated data; and comparing the differencing signal with a threshold signal. When the threshold signal has a value which approximately equals expected image noise, then the image data processed by a particular pixel may be deemed non-moving when the difference signal is less than the threshold signal, and the image data may be deemed to depict moving objects otherwise. Finally, image data is conducted unprocessed to the display for moving scene pixels, while frame integrated image data is conducted to the display for stationary scene pixels.

Abstract: A segment labeler/extractor outputs segments of video data stored in Random Access Memory for feature extraction and classification as targets. This function is accomplished by labeling the segments of a video frame as the segments are stored in a mass segment memory, sorting the mass segment memory to extract individual segment data, and storing this data in a segment memory where it can be accessed by an algorithm processor. Included in the subject invention is a segment labeler which consists of a segment label filter, adjacent label filter, memory, and sorter. The inputs to the segment labeler are a segment designator discrete which is set for only pixels which are in segments and a segment boundary designation discrete which is set for only pixels which are in segments and on the perimeter of the segment. The output of the segment labeler is a unique group of labels which define each segment. The groups of labels are then passed on to a control processor and handed to a segment extractor upon request.