Abstract: Buffering circuitry (10) uses pull-up slew rate control circuitry (12) and pull-down slew rate control circuitry (14) to control the rising and falling slew rates of an output signal (50) provided by buffering circuitry (10). Pull-up slew rate control circuitry (12) and pull-down slew rate control circuitry (14) may be used in an embodiment of buffering circuitry (10) which provides a higher output voltage VHIGH than the standard power voltage VPOWER which is used to power most of the circuitry. Buffering circuitry (10) utilizes distributed resistive elements (89-91) to provide improved electrostatic discharge protection. Buffering circuitry (10) utilizes a low power level shifter (16). Voltage reference generation circuitry (18) may be used to provide a stable low power reference voltage VREF (42).

Abstract: Buffering circuitry (10) uses pull-up slew rate control circuitry (12) and pull-down slew rate control circuitry (14) to control the rising and falling slew rates of an output signal (50) provided by buffering circuitry (10). Pull-up slew rate control circuitry (12) and pull-down slew rate control circuitry (14) may be used in an embodiment of buffering circuitry (10) which provides a higher output voltage VHIGH than the standard power voltage VPOWER which is used to power most of the circuitry. Buffering circuitry (10) utilizes distributed resistive elements (89-91) to provide improved electrostatic discharge protection. Buffering circuitry (10) utilizes a low power level shifter (16). Voltage reference generation circuitry (18) may be used to provide a stable low power reference voltage VREF (42).

Abstract: A tuning circuit (10) and method of operation for tuning an analog filter (40). The tuning circuit (10) has an integrator with an input portion (12) and a comparator portion (14), a counter (32), and a decoder (34). The integrator is implemented with an RC time constant which is proportional to an RC time constant of the analog filter (40). The comparator portion (14) provides an enable signal during the RC time constant of the integrator to the counter (16) which quantizes the RC time constant relative to a clock period of the counter (16). A predetermined decoding is performed to provide an output control signal to control adjustment of the RC time constant of the analog filter (40).

Abstract: An output driver circuit with improved output stage clamping comprises an input stage, an output stage, and a clamping circuit. The input stage amplifies a difference between an input signal and a reference signal to provide first and second output signals for driving gates of first and second transistors which together form the output stage. The first and second transistors are serially coupled between first and second power supply voltage terminals and provide an output signal. The clamping circuit clamps the first signal at a predetermined gate-to-source voltage below the first power supply voltage, and clamps the second signal at a predetermined gate-to-source voltage above the second power supply voltage terminal. The clamp voltages are maintained by matching current densities and bias conditions between the first and second transistors, and corresponding transistors in the clamping circuit.

Abstract: An analog-to-digital converter utilizes both a successive approximation register and a current steering circuit within a digital-to-analog converter to achieve an improved conversion speed, and improved resolution for a predetermined amount of power. The current steering circuit, which is controlled by the successive approximation register, connects constant current sources to current source loads to produce a differential signal output. By steering current from the differential current source loads to the constant current sources, a signal difference resolves at the output of the digital-to-analog converter faster and with greater resolution.

Abstract: A current source circuit providing a constant output for wide variations in supply voltages is achieved by creating a constant reference current by reflecting the difference in the base to emitter voltage of two bipolar transistors across a resistor. A first current mirror creates an equal current which flows through two diode connected transistors that produce an output voltage proportional to the current flowing through them. This current also flows through a second current mirror which creates an equal current to flow to a feedback connection. The feedback connection adjusts the base voltage of the two bipolar transistors until a current equal to the reference current flows in a third current mirror. The current flowing in this third current mirror is also applied to the feedback connection to insure that all currents remain equal thereby insuring the output remains constant.

Abstract: A slew rate limited output driver circuit has an output terminal which varies between two power supply voltage levels in response to an input data signal. The output signal is slew rate limited by a capacitor. In order to prevent a full range of the output voltage from being placed across the capacitor, the voltage across the capacitor is limited to only one-half the full range by forcing one electrode of the capacitor to remain at a voltage potential equal to a reference voltage which, in one form, is substantially halfway between the two power supply voltages.

Abstract: A high gate output stage for use with an amplifier which has high power supply rejection and which is stable at all frequencies is provided. An output current source and current sink are connected in series with a Miller capacitor coupled between an input terminal and output terminal of the output stage. Error signals coupled from a power supply source are allowed to sum at the output terminal with a compensating signal. Compensation circuitry is coupled to the input terminal for charge coupling a substantially equal but opposite amount of compensation charge related to the error signal from the power supply, thereby substantially cancelling power supply error signal coupling. Therefore, excellent power supply rejection and frequency stability are provided in a high gain output stage.

Abstract: A switched capacitor integrator for receiving a single input signal is compensated for parasitic capacitance errors with a minimum amount of circuitry. Although a single-ended amplifier is provided, a differential amplifier input is used which receives equal amounts of parasitic charge to effectively cancel charge errors. The size of the compensating capacitive circuitry may be reduced by making the input parasitic capacitance at one of the inputs proportionately larger so that the noise gain in both positive and negative signal paths remains substantially the same.

Abstract: An operational amplifier having differential inputs and differential outputs with a predetermined common-mode output voltage independent of common-mode input voltage and input voltage variation is provided. D.C. common-mode feedback is utilized to provide a differential amplifier having a precise common-mode output voltage.

Abstract: An amplifier circuit minimizes output voltage transients during powering up of the circuit. First and second bias current source portions are coupled to an input portion for receiving an input voltage. An amplifier portion is coupled to the input portion. The first bias current source portion provides a constant minimal current to the input portion which maintains the circuit bias voltage to the amplifier portion at near quiescent operating conditions. The second bias current source portion is switched to the input portion in response to a power control signal and provides bias current to the input portion necessary for circuit operation.

Abstract: An MOS analog switch utilizing two transmission gates which are compensated by a third transmission gate is provided. The transmission gates may be either single or complementary conductivity type transmission gates and are controlled by complementary clock signals. A method and apparatus for minimizing clock skew thereby reducing error voltages caused by parasitic capacitance are provided.

Abstract: An input buffer circuit having a single input for receiving input voltages characterized by having varying voltage swings is provided. First and second inverter circuits having differing switchpoint voltages are coupled to a level shifting position. The level shifting portion varies the level of swing of the input voltage and buffers the input voltage. In one form, voltage coupling circuitry is interposed between the level shifting portion and a latching portion which provides the input voltage as an output signal at a predetermined voltage level. In another form, voltage coupling circuitry controlled by control circuitry couples the output of the level shifting portion to an output in response to the input voltage.

Abstract: An output stage having a small quiescent current is provided. A current source portion provides an output current via an output terminal in proportion to a drive current. A current sink portion sinks output current in proportion to an input control voltage. A cross-over distortion portion and a shunt portion are coupled to the current source portion to minimize output quiescent current in proportion to the input control voltage.

Abstract: An on-chip voltage generator circuit is disclosed having an output voltage which is reduced by a predetermined amount from a supply voltage. The output voltage is proportional to the gate-to-source voltages of two complementary transistors and varies with temperature and processing in a similar manner with digital circuitry on the chip for which the output voltage may be used to operate. A current source is used to provide a known current to the two complementary transistors and a buffer is used to provide a low impedance output.

Abstract: A bias current reference circuit is disclosed having a first diode-connected bipolar device connected in series with an MOS device to develop a reference voltage which is proportional to a bias current. The reference voltage is used by an MOS device connected in series with a resistor which is connected in series with a second diode-connected bipolar device to develop a reference current which is proportional to the difference in the base to emitter voltages of the two bipolar devices. The reference current is used by a diode-connected MOS device to develop a bias voltage which is proportional to the reference current. The bias voltage in turn is used by another MOS device to develop the bias current in proportion to the bias voltage. The bias voltage is also used by other MOS devices to provide similar bias currents. In the disclosed embodiment, such a bias current can be used by a diode-connected CMOS device to develop a complementary bias voltage.

Abstract: A temperature stable bandgap voltage reference source utilizing two substrate bipolar transistors biased at different emitter current densities is provided. Switched capacitors are used to input the V.sub.be and the .DELTA.V.sub.be of the transistors (NTC and PTC voltages, respectively) into an amplifier to provide a reference voltage proportional to the weighted sum of the PTC and NTC voltages. Proper selection of the ratio of the switched capacitors renders the reference voltage substantially independent of temperature. In a modified form of the reference, the reference amplifier is implemented by an auto-zeroed operational amplifier which uses switched capacitor techniques and an integrated capacitor to achieve the auto-zeroing function.

Abstract: A temperature stable bandgap voltage reference source utilizing bipolar transistors biased at different emitter current densities is provided. Switched capacitors are used to input the V.sub.be and the .DELTA.V.sub.be of the transistors (PTC and NTC voltages, respectively,) into an operational amplifier to provide a reference voltage proportional to the sum of the PTC and NTC voltages. Proper selection of the ratio of the switched capacitors renders the reference voltage substantially independent of temperature. In a modified form of the reference, the reference amplifier is implemented by an auto-zeroed operational amplifier which uses switched capacitor techniques and an integrated capacitor to achieve the auto-zeroing function.

Abstract: A bias current reference circuit is disclosed having a diode-connected bipolar device connected in series with an MOS device to develop a reference voltage which is proportional to a bias current. The reference voltage is used by an MOS device connected in series with a resistor to develop a reference current which is proportional to the reference voltage. The reference current is used by a diode-connected MOS device to develop a bias voltage which is proportional to the reference current. The bias voltage in turn is used by another MOS device to develop the bias current in proportion to the bias voltage. The bias voltage is also used by other MOS devices to provide similar bias currents. In the disclosed embodiment, such a bias current is used by a complementary diode-connected MOS device to develop a complementary bias voltage. The complementary bias voltage may be used to develop start-up bias current in the event the bias current reference circuit fails to provide a suitable bias voltage.

Abstract: A driver circuit suitable for use in an operational amplifier, includes a bipolar pull-up transistor which sources current to an output terminal in proportion to an applied drive current, and an MOS pull-down transistor which sinks current from the output terminal in proportion to an applied control voltage. An MOS drive transistor provides a constant drive current for the pull-up transistor, and an MOS shunt transistor shunts the drive current away from the bipolar transistor in proportion to the control voltage. A cross-over compensation circuit develops a predetermined bias voltage on the base of the bipolar transistor relative to the voltage on the output terminal, to assure a minimum level of operation of the bipolar transistor when the output terminal is near the analog ground voltage.