Patents by Inventor Roger Aime Dufresne

Roger Aime Dufresne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Negative differential resistance reoxidized nitride silicon-based photodiode and method
    Patent number: 6743655
    Abstract: A photodiode that exhibits a photo-induced negative differential resistance region upon biasing and illumination is described. The photodiode includes an N+ silicon substrate, a silicon nitride layer formed on the N+ silicon substrate, a reoxidized nitride layer formed on the silicon nitride layer and a N+ polysilicon layer formed on at least a portion of the reoxidized nitride layer.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: June 1, 2004
    Assignee: International Business Machines Corporation
    Inventors: Fen Chen, Roger Aime Dufresne, Baozhen Li, Alvin Wayne Strong
  • Negative differential resistance reoxidized nitride silicon-based photodiode and method
    Publication number: 20020185703
    Abstract: A photodiode that exhibits a photo-induced negative differential resistance region upon biasing and illumination is described. The photodiode includes an N+ silicon substrate, a silicon nitride layer formed on the N+ silicon substrate, a reoxidized nitride layer formed on the silicon nitride layer and a N+ polysilicon layer formed on at least a portion of the reoxidized nitride layer.
    Type: Application
    Filed: July 25, 2002
    Publication date: December 12, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fen Chen, Roger Aime Dufresne, Baozhen Li, Alvin Wayne Strong
  • Negative differential resistance reoxidized nitride silicon-based photodiode and method
    Patent number: 6445021
    Abstract: A photodiode that exhibits a photo-induced negative differential resistance region upon biasing and illumination is described. The photodiode includes an N+ silicon substrate, a silicon nitride layer formed on the N+ silicon substrate, a reoxidized nitride layer formed on the silicon nitride layer and a N+ polysilicon layer formed on at least a portion of the reoxidized nitride layer.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: September 3, 2002
    Assignee: International Business Machines Corporation
    Inventors: Fen Chen, Roger Aime Dufresne, Baozhen Li, Alvin Wayne Strong
  • Structure and method for reliability stressing of dielectrics
    Patent number: 5898706
    Abstract: The present invention is directed to an apparatus and method for reliability testing of an integrated circuit. The present invention provides a test structure and method for testing gate and node dielectrics of an integrated circuit wherein a self-heating gate structure is integrated with the product structure itself. Selected conductive lines within the product structure are used as heater elements to provide temperature stressing of the integrated circuit. The localized self-heating gate structure is an integral part of the product chip. Thus, etch and deposition characteristics of the test structure are kept identical to the etch and deposition characteristics of the product itself. As low-voltage technologies make it harder to obtain significant acceleration due to voltage stressing, temperature stressing may be used instead to increase acceleration.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: April 27, 1999
    Assignee: International Business Machines Corporation
    Inventors: Roger Aime Dufresne, Charles William Griffin, Chorng-Lii Hwang, William Alan Klaasen, Alvin Wayne Strong