Patents by Inventor Roger Allan Quon

Roger Allan Quon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SELECTIVE ION FILTERING IN A MULTIPURPOSE CHAMBER
    Publication number: 20200066491
    Abstract: A multipurpose semiconductor process chamber includes a vessel wall that encloses contiguous first and second volumes of the multipurpose chamber, and means for selectively effectively preventing ions moving across a plane that partitions the first volume from the second volume. For example, the means can include an electromagnet, or at least one permanent magnet, that is operable to impose and remove a magnetic field with field lines extending in the plane.
    Type: Application
    Filed: November 4, 2019
    Publication date: February 27, 2020
    Inventors: Lawrence A. Clevenger, Roger Allan Quon, Theodorus E. Standaert, Wei Wang, Chih-Chao Yang
  • SELECTIVE ION FILTERING IN A MULTIPURPOSE CHAMBER
    Publication number: 20190355555
    Abstract: A multipurpose semiconductor process chamber includes a vessel wall that encloses contiguous first and second volumes of the multipurpose chamber, and means for selectively effectively preventing ions moving across a plane that partitions the first volume from the second volume. For example, the means can include an electromagnet, or at least one permanent magnet, that is operable to impose and remove a magnetic field with field lines extending in the plane.
    Type: Application
    Filed: May 18, 2018
    Publication date: November 21, 2019
    Inventors: Lawrence A. Clevenger, Roger Allan Quon, Theodorus E. Standaert, Wei Wang, Chih-Chao Yang
  • Selective ion filtering in a multipurpose chamber
    Patent number: 10483091
    Abstract: A multipurpose semiconductor process chamber includes a vessel wall that encloses contiguous first and second volumes of the multipurpose chamber, and means for selectively effectively preventing ions moving across a plane that partitions the first volume from the second volume. For example, the means can include an electromagnet, or at least one permanent magnet, that is operable to impose and remove a magnetic field with field lines extending in the plane.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Roger Allan Quon, Theodorus E. Standaert, Wei Wang, Chih-Chao Yang
  • Structure and method for improved stabilization of cobalt cap and/or cobalt liner in interconnects
    Patent number: 10134674
    Abstract: A method of fabricating a metallization layer of a semiconductor device in which copper is used for an interconnect material and cobalt is used to encapsulate the copper. A material is introduced that will interact with the cobalt to cause a hexagonal-close-packed (HCP) crystal structure of cobalt to change to a face-centered-cubic (FCC) crystal structure of cobalt, the FCC crystal structure providing a resistance of the cobalt to migrate.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, James J. Kelly, Koichi Motoyama, Roger Allan Quon, Michael Rizzolo, Theodorus Eduardus Standaert
  • STRUCTURE AND METHOD FOR IMPROVED STABILIZATION OF COBALT CAP AND/OR COBALT LINER IN INTERCONNECTS
    Publication number: 20180005953
    Abstract: A method of fabricating a metallization layer of a semiconductor device in which copper is used for an interconnect material and cobalt is used to encapsulate the copper. A material is introduced that will interact with the cobalt to cause a hexagonal-close-packed (HCP) crystal structure of cobalt to change to a face-centered-cubic (FCC) crystal structure of cobalt, the FCC crystal structure providing a resistance of the cobalt to migrate.
    Type: Application
    Filed: August 14, 2017
    Publication date: January 4, 2018
    Inventors: Benjamin D. Briggs, James J. Kelly, Koichi Motoyama, Roger Allan Quon, Michael Rizzolo, Theodorus Eduardus Standaert
  • Structure and method for improved stabilization of cobalt cap and/or cobalt liner in interconnects
    Patent number: 9780035
    Abstract: A method for fabricating a metallization layer of a semiconductor device, in which copper is used for an interconnect material and cobalt is used to encapsulate the copper, includes introducing a material that will form an alloy with cobalt and resist a degradation of an effect of the cobalt on encapsulating the copper.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, James J. Kelly, Koichi Motoyama, Roger Allan Quon, Michael Rizzolo, Theodorus Eduardus Standaert
  • Method and system to predict lithography focus error using simulated or measured topography
    Patent number: 8792080
    Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: July 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian Christopher Sapp, Choongyeun Cho, Lawrence A. Clevenger, Laertis Economikos, Bernhard R. Liegl, Kevin S. Petrarca, Roger Allan Quon
  • METHOD AND SYSTEM TO PREDICT LITHOGRAPHY FOCUS ERROR USING SIMULATED OR MEASURED TOPOGRAPHY
    Publication number: 20140075396
    Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.
    Type: Application
    Filed: November 15, 2013
    Publication date: March 13, 2014
    Applicant: International Business Machines Corporation
    Inventors: Choongyeun Cho, Lawrence A. Clevenger, Laertis Economikos, Bernhard R. Liegl, Kevin S. Petrarca, Roger Allan Quon, Brian Christopher Sapp
  • METHOD AND SYSTEM TO PREDICT LITHOGRAPHY FOCUS ERROR USING SIMULATED OR MEASURED TOPOGRAPHY
    Publication number: 20140075399
    Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.
    Type: Application
    Filed: November 15, 2013
    Publication date: March 13, 2014
    Inventors: Choongyeun Cho, Lawrence A. Clevenger, Laertis Economikos, Bernhard R. Liegl, Kevin S. Petrarca, Roger Allan Quon, Brian Christopher Sapp
  • METHOD AND SYSTEM TO PREDICT LITHOGRAPHY FOCUS ERROR USING SIMULATED OR MEASURED TOPOGRAPHY
    Publication number: 20140071416
    Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.
    Type: Application
    Filed: November 15, 2013
    Publication date: March 13, 2014
    Inventors: Choongyeun Cho, Lawrence A. Clevenger, Laertis Economikos, Bernhard R. Liegl, Kevin S. Petrarca, Roger Allan Quon, Brian Christopher Sapp
  • METHOD AND SYSTEM TO PREDICT LITHOGRAPHY FOCUS ERROR USING SIMULATED OR MEASURED TOPOGRAPHY
    Publication number: 20120194792
    Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.
    Type: Application
    Filed: January 27, 2011
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian Christopher Sapp, Choongyeun Cho, Lawrence A. Clevenger, Laertis Economikos, Bernhard R. Liegl, Kevin S. Petrarca, Roger Allan Quon