Abstract: A network processor or other type of processor includes an interface comprising a plurality of signal lines, and interface circuitry adapted to receive clock signals for respective interface clock domains of the processor. The interface circuitry comprises a plurality of sampling registers clocked by respective ones of the clock signals. The interface circuitry is configurable in a variety of different configurations, each providing a different association between designated subsets of the signal lines and the clock domains of the processor.

Abstract: A clock generator circuit for use with a low power data storage unit includes a resonator circuit for providing a first output frequency resonating at a fundamental frequency of a quartz crystal. A frequency multiplication circuit for multiplies the first output frequency by a predetermined factor to produce a second output frequency greater than the first output frequency. This second output frequency is coupled to the data storage unit and is used during normal read/write mode of operation. In a low power mode of operation, a switching network couples the first output frequency directly to the data storage unit so as to reduce the overall power consumption.