Patents by Inventor Roger Bettman
Roger Bettman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230197128Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.Type: ApplicationFiled: February 13, 2023Publication date: June 22, 2023Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
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Patent number: 11581029Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.Type: GrantFiled: April 30, 2021Date of Patent: February 14, 2023Assignee: LONGITUDE ELASH MEMORY SOLUTIONS LTDInventors: Cristinel Zonte, Vijay Raghavan, Iulian C Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
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Publication number: 20210327477Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.Type: ApplicationFiled: April 30, 2021Publication date: October 21, 2021Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C. Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
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Patent number: 10998019Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.Type: GrantFiled: December 16, 2019Date of Patent: May 4, 2021Assignee: Longitude Flash Memory Solutions, Ltd.Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C. Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
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Publication number: 20200234746Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.Type: ApplicationFiled: December 16, 2019Publication date: July 23, 2020Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C. Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
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Patent number: 10062423Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.Type: GrantFiled: September 16, 2016Date of Patent: August 28, 2018Assignee: Cypress Semiconductor CorporationInventors: Cristinel Zonte, Vijay Raghavan, Iulian C. Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
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Patent number: 10020034Abstract: Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.Type: GrantFiled: March 20, 2017Date of Patent: July 10, 2018Assignee: Cypress Semiconductor CorporationInventors: Vineet Agrawal, Roger Bettman, Samuel Leshner
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Publication number: 20170249978Abstract: Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.Type: ApplicationFiled: March 20, 2017Publication date: August 31, 2017Applicant: Cypress Semiconductor CorporationInventors: Vineet Agrawal, Roger Bettman, Samuel Leshner
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Patent number: 9627016Abstract: Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.Type: GrantFiled: December 22, 2015Date of Patent: April 18, 2017Assignee: Cypress Semiconductor CorporationInventors: Vineet Agrawal, Roger Bettman, Samuel Leshner
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Publication number: 20170098468Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.Type: ApplicationFiled: September 16, 2016Publication date: April 6, 2017Inventors: Cristinel Zonte, Vijay Raghavan, Iulian C. Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
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Publication number: 20170076766Abstract: Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.Type: ApplicationFiled: December 22, 2015Publication date: March 16, 2017Applicant: Cypress Semiconductor CorporationInventors: Vineet Agrawal, Roger Bettman, Samuel Leshner
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Patent number: 9472511Abstract: An ESD device that includes a gate and an n-drain region isolated from the gate and formed at least partially within an n-well region, which in turn is formed at least partially within a deep n-well region. The doping levels of the n-drain region, the n-well region and the deep n-well region are in a descending order. The ESD device has trigger and holding voltages, above the operation voltage of its protected circuit, which are layout-configurable by altering the distance between the n-drain and a side edge of the n-well region.Type: GrantFiled: December 4, 2014Date of Patent: October 18, 2016Assignee: Cypress Semiconductor CorporationInventors: Sungkwon Lee, Roger Bettman, Sai Prashanth Dhanraj, Dung Ho, Leo F Luquette, Jr., Iman Rezanezhad Gatabi, Andrew Walker
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Patent number: 9449655Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.Type: GrantFiled: December 11, 2015Date of Patent: September 20, 2016Assignee: Cypress Semiconductor CorporationInventors: Cristinel Zonte, Vijay Raghavan, Iulian C. Gradinariu, Gary Peter Moscaluk, Roger Bettman, Vineet Argrawal, Samuel Leshner
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Publication number: 20150200168Abstract: An ESD device that includes a gate and an n-drain region isolated from the gate and formed at least partially within an n-well region, which in turn is formed at least partially within a deep n-well region. The doping levels of the n-drain region, the n-well region and the deep n-well region are in a descending order. The ESD device has trigger and holding voltages, above the operation voltage of its protected circuit, which are layout-configurable by altering the distance between the n-drain and a side edge of the n-well region.Type: ApplicationFiled: December 4, 2014Publication date: July 16, 2015Inventors: Sungkwon Lee, Roger Bettman, Sai Prashanth Dhanraj, Dung Ho, Leo F. Luquette, JR., Iman Rezanezhad Gatabi, Andrew Walker
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Patent number: 7307861Abstract: A ternary content addressable memory (TCAM) cell (100) can include two memory elements (102-0 and 102-1) with a single bit line (106-0 and 106-1) per memory element. A TCAM cell (100) can also include a compare stack (104) and two word lines (114 and 116) that can connect to each memory element (102-0 and 102-1). The memory elements (102-0 and 102-1) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements (102-0 and 102-1) to the pre-write potential prior to providing write data via the bit lines (106-0 and 106-1).Type: GrantFiled: December 28, 2006Date of Patent: December 11, 2007Assignee: Netlogic Microsystems, Inc.Inventors: Roger Bettman, Eric H. Voelkel
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Patent number: 7173837Abstract: A ternary content addressable memory (TCAM) cell (100) can include two memory elements (102-0 and 102-1) with a single bit line (106-0 and 106-1) per memory element. A TCAM cell (100) can also include a compare stack (104) and two word lines (114 and 116) that can connect to each memory element (102-0 and 102-1). The memory elements (102-0 and 102-1) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements (102-0 and 102-1) to the pre-write potential prior to providing write data via the bit lines (106-0 and 106-1).Type: GrantFiled: August 31, 2004Date of Patent: February 6, 2007Assignee: Netlogic Microsystems, Inc.Inventors: Roger Bettman, Eric H. Voelkel
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Patent number: 6708190Abstract: A programmable logic device comprising one or more macrocells and a product term array. The macrocells may comprise logic that may be configured to (i) generate and propagate a carry signal and (ii) generate a sum bit. The product term array may comprise two product terms per macrocell.Type: GrantFiled: June 5, 2000Date of Patent: March 16, 2004Assignee: Cypress Semiconductor Corp.Inventors: Christopher W. Jones, Roger Bettman
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Patent number: 6486701Abstract: An apparatus comprises two or more memory elements connected in parallel and programmed alike, where the memory elements comprise a high speed path of a programmable logic device.Type: GrantFiled: June 12, 2000Date of Patent: November 26, 2002Assignee: Cypress Semiconductor Corp.Inventor: Roger Bettman
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Patent number: 6191607Abstract: A programmable bus hold circuit which may find application in programmable logic devices, memories and other I/O devices may include a first element for receiving a voltage from an I/O pad and programmable circuitry coupled to the first element for controlling whether the voltage at the pad is to be held its current logic level. The first element may be a logic gate (such as a NOR gate) the programmable circuit may include a tristatable buffer (e.g., under the control of a memory cell or other programmable bit capable of enabling or disabling the programmable bus hold circuit) or a switch (e.g., a transistor).Type: GrantFiled: September 16, 1998Date of Patent: February 20, 2001Assignee: Cypress Semiconductor CorporationInventors: Anita X. Meng, Roger Bettman, Barry Loveridge
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Patent number: 6148435Abstract: One or more optimized programming or erase parameters is (are) determined for a programmable device and that parameter (or those parameters) is (are) stored in the programmable device. When the programmable device is to be programmed or erased, the optimized parameter (or parameters) is (are) read from the programmable device and used in the programming or erase process.Type: GrantFiled: December 24, 1997Date of Patent: November 14, 2000Assignee: Cypress Semiconductor CorporationInventor: Roger Bettman