Patents by Inventor Roger C. Jeppsen
Roger C. Jeppsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10990546Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.Type: GrantFiled: February 19, 2019Date of Patent: April 27, 2021Assignee: Intel CorporationInventors: Samantha J. Edirisooriya, Geetani R. Edirisooriya, Roger C. Jeppsen, Pankaj Kumar
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Publication number: 20190179786Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.Type: ApplicationFiled: February 19, 2019Publication date: June 13, 2019Inventors: Samantha J. Edirisooriya, Geetani R. Edirisooriya, Roger C. Jeppsen, Pankaj Kumar
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Patent number: 10241947Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.Type: GrantFiled: February 3, 2017Date of Patent: March 26, 2019Assignee: Intel CorporationInventors: Samantha J. Edirisooriya, Geetani R. Edirisooriya, Roger C. Jeppsen, Pankaj Kumar
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Publication number: 20180225237Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.Type: ApplicationFiled: February 3, 2017Publication date: August 9, 2018Inventors: Samantha J. Edirisooriya, Geetani R. Edirisooriya, Roger C. Jeppsen, Pankaj Kumar
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Patent number: 9953001Abstract: Method, apparatus, and system of detecting a hot-plug event. The hot-plug event detection may be done in-band or out-of-band. The in-band detection is performed by a state machine and the out-of-band detection is performed by a logic. A circuitry is to detect a hot-plug event when inserting or removing a device from an extension bus of the plurality of extension bus slots. The circuit is to generate a hot-plug message to notify the hot-plug event. The circuitry including the state machine, the logic and a register to provide at least two bits to mask at least two states of the state machine.Type: GrantFiled: April 1, 2016Date of Patent: April 24, 2018Assignee: INTEL CORPORATIONInventors: Samantha J. Edirisooriya, Roger C. Jeppsen, Pankaj Kumar, Blaine R. Monson
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Publication number: 20170286349Abstract: Method, apparatus, and system of detecting a hot-plug event. The hot-plug event detection may be done in-band or out-of-band. The in-band detection is performed by a state machine and the out-of-band detection is performed by a logic. A circuitry is to detect a hot-plug event when inserting or removing a device from an extension bus of the plurality of extension bus slots. The circuit is to generate a hot-plug message to notify the hot-plug event. The circuitry including the state machine, the logic and a register to provide at least two bits to mask at least two states of the state machine.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: Samantha J. Edirisooriya, Roger C. Jeppsen, Pankaj Kumar, Blaine R. Monson
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Publication number: 20160092118Abstract: In accordance with the present description, an apparatus for use with a source issuing write operations to a target, wherein the device includes an I/O port, and logic of the target configured to detect a flag issued by the source in association with the issuance of a first plurality of write operations. In response to detection of the flag, the logic of the target ensures that the first plurality of write operations are completed in a memory prior to completion of any of the write operations of the second plurality of write operations. Also described is an apparatus of the source which includes an I/O port, and logic of the source configured to issue the first plurality of write operations and to issue a write fence flag in association with the issuance of a first plurality of write operations. Other aspects are described herein.Type: ApplicationFiled: August 28, 2015Publication date: March 31, 2016Inventors: Pankaj KUMAR, Samantha J. EDIRISOORIYA, Roger C. JEPPSEN
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Publication number: 20160092123Abstract: In accordance with the present description, an apparatus for use with a source issuing write operations to a target, wherein the device includes an I/O port, and logic of the target configured to detect a flag issued by the source in association with the issuance of a first plurality of write operations. In response to detection of the flag, the logic of the target ensures that the first plurality of write operations are completed in a memory prior to completion of any of the write operations of the second plurality of write operations. Other aspects are described herein.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: Pankaj KUMAR, Samantha J. EDIRISOORIYA, Roger C. JEPPSEN
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Patent number: 7797465Abstract: A core of a network includes a storage unit to store a plurality of parameters to receive and transmit data packets in a communication system. A program controls transfer of the data packets between the core and a network node. The plurality of parameters in the storage unit controls the receiving and transmitting.Type: GrantFiled: June 10, 2005Date of Patent: September 14, 2010Assignee: Intel CorporationInventors: Roger C. Jeppsen, Nathan Marushak, Brian J. Skerry, Jeffrey D. Skirvin
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Patent number: 7506078Abstract: A method according to one embodiment may include discovering at least one ATA/ATAPI target device. The method of this embodiment may also include discovering a SAS address for at the least one ATA/ATAPI target device. The method of this embodiment may also include returning the SAS address for the at least one ATA/ATAPI target device in response to a device inquiry command. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.Type: GrantFiled: October 29, 2004Date of Patent: March 17, 2009Assignee: Intel CorporationInventors: Jonathan Wootten, Roger C. Jeppsen, Nathan E. Marushak, Brian Skerry
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Patent number: 7366958Abstract: One embodiment of a method may include, in response, at least in part, to one or more received frames, generating an interrupt and preventing transmission of one or more other frames. The one or more received frames may indicate, at least in part, an error condition or a commencement of a data transfer. The method of this embodiment also may include, in response, at least in part, to the interrupt, executing one or more instructions. The one or more instructions, when executed, may optionally result in deleting the one or more other frames, and if the one or more received frames indicate, at least in part, the error condition, commencing recovery from the error condition. If the one or more received frames indicate, at least in part, the commencement of the data transfer, the method of the embodiment may include storing data associated with the data transfer.Type: GrantFiled: December 14, 2004Date of Patent: April 29, 2008Assignee: Intel CorporationInventors: Nathan E. Marushak, Roger C. Jeppsen, Richard C. Beckett, Devicharan Devidas, Richard D. Carmichael
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Patent number: 7032042Abstract: In one embodiment, a method may include, if an amount of data requested to be transferred by a data transfer request according to a first protocol exceeds a maximum data transfer amount permitted to be requested by a single data transfer request according to a second protocol, generating one data transfer request according to the second protocol and a data structure, and modifying, at least in part, another data structure. This data transfer request may request transfer of a portion of the data. The data structure may include one or more values identifying, at least in part, another portion of the data. The modifying may be based, at least in part, upon the one or more values. The other data structure may include, prior to being modified, one or more other values indicating, at least in part, one or more parameters of the one data transfer request.Type: GrantFiled: September 10, 2003Date of Patent: April 18, 2006Assignee: Intel CorporationInventors: Roger C. Jeppsen, Nathan E. Marushak