Patents by Inventor Roger Chang
Roger Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250063653Abstract: An electronic device is provided, including a substrate, a conductive element, and an insulating layer. The conductive element is disposed on the substrate and has a side wall. The conductive element includes a first layer and a second layer. The second layer is disposed on the first layer. The insulating layer is disposed on the conductive element. A thickness of the second layer is greater than a thickness of the first layer. At least a portion of the side wall is uneven, and a portion of the insulating layer is disposed corresponding to the side wall.Type: ApplicationFiled: October 31, 2024Publication date: February 20, 2025Inventors: Roger HUANG, Joe HUANG, Lavender CHENG, Sean CHANG
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Publication number: 20240382903Abstract: A replaceable membrane distillation module has a membrane distillation plate with an upper portion and a lower portion at two ends respectively. Two upper holes and two lower holes are defined through the upper portion and the lower portion at two ends respectively. A distillation portion is recessed in at least one side of the membrane distillation plate, and a distillation membrane covers on the distillation portion that a distillation space forms between the distillation portions and the distillation membrane. Multiple channels are disposed in the membrane distillation plate to communicate one of the upper holes, the distillation space and one of the lower flow holes. A blocking element is selectively combined with one of the upper holes or one of the lower flow holes.Type: ApplicationFiled: December 8, 2023Publication date: November 21, 2024Inventors: Roger CHANG, Po-Chun SHIH, Hong-Yi WANG, Ting Yun WU
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Patent number: 10676671Abstract: The present invention relates to a method of reducing ODF mura in liquid crystal (LC) displays of the polymer sustained alignment (PSA) type and to PSA LC displays made by this method.Type: GrantFiled: June 23, 2016Date of Patent: June 9, 2020Assignee: Merck Patent GmbHInventors: Leo Weegels, Roger Chang, Ky Lin
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Publication number: 20180201837Abstract: The present invention relates to a method of reducing ODF mura in liquid crystal (LC) displays of the polymer sustained alignment (PSA) type and to PSA LC displays made by this method.Type: ApplicationFiled: June 23, 2016Publication date: July 19, 2018Applicant: Merck Patent GmbHInventors: Leo WEEGELS, Roger CHANG, Ky LIN
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Publication number: 20160230475Abstract: A drilling riser buoyancy module comprises two opposite complementary halves each having complementary co-axially extending central opening for a flow line and at least five complementary axially extending secondary openings for receiving auxiliary lines. Each complementary half comprising foam bounded by an interior surface and an exterior surface. A portion of the interior surfaces of complementary halves contact each another.Type: ApplicationFiled: February 8, 2016Publication date: August 11, 2016Inventors: Majdi Haddad, Roger Chang, Mark Schlegel, Louis Kabelka
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Publication number: 20130037745Abstract: The present invention relates to a liquid-crystalline medium, characterised in that it contains a polymerisable component (A) containing one more polymerisable compounds and a liquid-crystalline component (B) containing one more compounds of the general formula I and/or IA in which R0, X0 and L1-6 have the meanings indicated in Claim 1, and to the use thereof in electro-optical liquid-crystal displays.Type: ApplicationFiled: August 8, 2012Publication date: February 14, 2013Applicant: MERCK PATENT GESELLSCHAFT MIT BESCHRANKTER HAFTUNGInventors: Gavin HUNG, Roger CHANG, Kris TSAI, Glavin OYANG
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Patent number: 7892412Abstract: A manufacturing process of an embedded type flexible or rigid printed circuit board includes multiple steps. First, a layer of dry film is applied to a layer of copper foil. Then a circuit pattern is formed on the copper foil through photolithography processes. An etching stop layer is electroplated on the copper foil according to the circuit pattern. The etching stop layer is then electroplated with copper. The copper foil is softened by a high temperature process after removing the dry film. Then the layer of the copper foil is etched after coating with an organic layer and the organic layer is solidified.Type: GrantFiled: September 6, 2007Date of Patent: February 22, 2011Assignee: Mutual-Tek Industries Co., Ltd.Inventor: Roger Chang
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Patent number: 7844892Abstract: The invention provides improved mechanisms for the construction and rendering of graphical results sets for business intelligence reports derived from large volumes of data. This is achieved by various means including, determining the amount of useful data that can be rendered within the available display space while still being legible, determining the most effective way of displaying that data within the display space, and providing for limited control of the format and quantity of data displayed.Type: GrantFiled: August 17, 2006Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: Nadia Shewchenko, Henning Hoffmann, Roger Chang, Lesley Grignon
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Patent number: 7603771Abstract: A method of providing at least two multilayer circuit boards, combining the at least two multilayer circuit boards to form a combined multilayer circuit board, and forming multiple outer conductive vias, circuits and contacts on the combined multilayer circuit board. Each multilayer circuit board is fabricated by the steps of preparing a single-layer printed circuit board having multiple chip sections, attaching at least one chip to the corresponding chip section, attaching a frame having multiple enclosures to the single-layer printed circuit board, attaching a semi-fluid glue sheet to the frame, vacuum pressing a conductive layer on the semi-fluid glue sheet and forming multiple conductive inner vias through the multilayer circuit board. The at least two multilayer circuit boards are combined by steps of reversing one of the multilayer circuit boards and vacuum pressing other multilayer circuit boards on the reversed multilayer circuit board.Type: GrantFiled: August 29, 2006Date of Patent: October 20, 2009Assignee: Mutual-Tek Industries Co., Ltd.Inventor: Roger Chang
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Patent number: 7505282Abstract: A multilayer circuit board has a bottom and an upper multilayer circuit boards, a glue layer, multiple outer contact vias and two insulating lacquer layers. The bottom and the upper multilayer circuit boards respectively have multiple conductive wires, an insulating layer, a frame, multiple chips, a press laminate, a patterned conductive layer and at least one inner contact via. The glue layer sticks the bottom and the upper multilayer circuit boards together. The multiple contact vias are formed through the bottom and the upper multilayer circuit boards to electronically interconnect the conductive wires and the patterned conductive layers in the bottom and the upper multilayer circuit boards. The insulating lacquer layers are respectively coated under and on portions of the patterned conductive layers in the bottom and the upper multilayer circuit boards to protect the patterned conductive layers, wherein the un-coated patterned conductive layers become multiple contacts.Type: GrantFiled: October 31, 2006Date of Patent: March 17, 2009Assignee: Mutual-TEK Industries Co., Ltd.Inventor: Roger Chang
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Publication number: 20090056118Abstract: A method has acts of providing at least two multilayer circuit boards, combining the at least two multilayer circuit boards to form a combined multilayer circuit board, forming multiple outer conductive vias, circuits and contacts on the combined multilayer circuit board. Each multilayer circuit board is fabricated by steps of preparing a single-layer printed circuit board having multiple chip sections, attaching at least one chip to the corresponding chip section, attaching a frame having multiple enclosures to the single-layer printed circuit board, attaching a semi-fluid glue sheet to the frame, vacuum pressing a conductive layer on the semi-fluid glue sheet and forming multiple conductive inner vias through the multilayer circuit board. The at least two multilayer circuit boards are combined by steps of reversing one of the multilayer circuit boards and vacuum pressing other multilayer circuit boards on the reversed multilayer circuit board.Type: ApplicationFiled: October 31, 2008Publication date: March 5, 2009Inventor: Roger CHANG
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Publication number: 20080101044Abstract: A multilayer circuit board has a bottom and an upper multilayer circuit boards, a glue layer, multiple outer contact vias and two insulating lacquer layers. The bottom and the upper multilayer circuit boards respectively have multiple conductive wires, an insulating layer, a frame, multiple chips, a press laminate, a patterned conductive layer and at least one inner contact via. The glue layer sticks the bottom and the upper multilayer circuit boards together. The multiple contact vias are formed through the bottom and the upper multilayer circuit boards to electronically interconnect the conductive wires and the patterned conductive layers in the bottom and the upper multilayer circuit boards. The insulating lacquer layers are respectively coated under and on portions of the patterned conductive layers in the bottom and the upper multilayer circuit boards to protect the patterned conductive layers, wherein the un-coated patterned conductive layers become multiple contacts.Type: ApplicationFiled: October 31, 2006Publication date: May 1, 2008Inventor: Roger Chang
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Publication number: 20080057627Abstract: A method has acts of providing at least two multilayer circuit boards, combining the at least two multilayer circuit boards to form a combined multilayer circuit board, forming multiple outer conductive vias, circuits and contacts on the combined multilayer circuit board. Each multilayer circuit board is fabricated by steps of preparing a single-layer printed circuit board having multiple chip sections, attaching at least one chip to the corresponding chip section, attaching a frame having multiple enclosures to the single-layer printed circuit board, attaching a semi-fluid glue sheet to the frame, vacuum pressing a conductive layer on the semi-fluid glue sheet and forming multiple conductive inner vias through the multilayer circuit board. The at least two multilayer circuit boards are combined by steps of reversing one of the multilayer circuit boards and vacuum pressing other multilayer circuit boards on the reversed multilayer circuit board.Type: ApplicationFiled: August 29, 2006Publication date: March 6, 2008Inventor: Roger Chang
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Publication number: 20080046805Abstract: The invention provides improved mechanisms for the construction and rendering of graphical results sets for business intelligence reports derived from large volumes of data. This is achieved by various means including, determining the amount of useful data that can be rendered within the available display space while still being legible, determining the most effective way of displaying that data within the display space, and providing for limited control of the format and quantity of data displayed.Type: ApplicationFiled: August 17, 2006Publication date: February 21, 2008Applicant: Cognos IncorporatedInventors: Nadia Shewchenko, Henning Hoffmann, Roger Chang, Lesley Grignon
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Publication number: 20070295606Abstract: A manufacturing process of an embedded type flexible or rigid printed circuit board includes multiple steps. First, a layer of dry film is applied to a layer of copper foil. Then a circuit pattern is formed on the copper foil through photolithography processes. An etching stop layer is electroplated on the copper foil according to the circuit pattern. The etching stop layer is then electroplated with copper. The copper foil is softened by a high temperature process after removing the dry film. Then the layer of the copper foil is etched after coating with an organic layer and the organic layer is solidified.Type: ApplicationFiled: September 6, 2007Publication date: December 27, 2007Applicant: MUTUAL-TEK INDUSTRIES CO., LTD.Inventor: Roger Chang
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Patent number: 7297285Abstract: A manufacturing process of an emboss type flexible or rigid printed circuit board includes multiple steps. First, a layer of dry film is applied to a layer of copper foil. Then a circuit pattern is formed on the copper foil through photolithography processes. An etching stop layer is electroplated on the circuit pattern. The etching stop layer is then electroplated with copper. The copper foil is softened by a high temperature process after removing the dry film. Then the layer of the copper foil is etched after coating with an organic surface layer and the organic surface layer is solidified.Type: GrantFiled: August 5, 2005Date of Patent: November 20, 2007Inventor: Roger Chang
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Publication number: 20070029204Abstract: A manufacturing process of an emboss type flexible or rigid printed circuit board includes multiple steps. First, a layer of dry film is applied to a layer of copper foil. Then a circuit pattern is formed on the copper foil through photolithography processes. An etching stop layer is electroplated on the circuit pattern. The etching stop layer is then electroplated with copper. The copper foil is softened by a high temperature process after removing the dry film. Then the layer of the copper foil is etched after coating with an organic surface layer and the organic surface layer is solidified.Type: ApplicationFiled: August 5, 2005Publication date: February 8, 2007Inventor: Roger Chang
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Publication number: 20060005112Abstract: A conditional layout system for rendering and formatting content in a report is provided. The conditional layout system comprises an element receiving unit for receiving a variable element referenced in a report element, a condition processing unit for calculating a condition value based upon an expression in the variable element, and an element rendering unit for conditionally rendering and formatting report elements based upon the condition value.Type: ApplicationFiled: July 2, 2004Publication date: January 5, 2006Inventors: David Lilly, Eric McCully, Roger Chang
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Patent number: 6978817Abstract: A method for manufacturing a fluoropolymer compound plate comprises the steps of: combining a fluoropolymer sheet and a medium plate as a fluoropolymer compound plate; transferring the fluoropolymer compound plate to a preheat section for being heated uniformly in a lower tension, transferring the fluoropolymer compound plate to a melting section for heating the fluoropolymer sheet of the fluoropolymer compound plate; transferring the fluoropolymer compound plate to a pressing section by rollers; and compressing and annealing the fluoropolymer compound plate. A device for performing the method comprises a plurality of tension adjusting axial seats; a plurality of roller; a pair of first guide wheels; an upper and a lower layer radiating heater; a third guide wheel set; an upper and a lower layer high temperature radiating heater; a guiding roller; a shaping heater; a plurality of temperature controller roller sets and a product winding wheel.Type: GrantFiled: February 17, 2003Date of Patent: December 27, 2005Assignee: Allied Supreme CorpInventors: Amber Ho, Roger Chang
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Publication number: 20050275081Abstract: An embedded chip semiconductor has a substrate, at least one chip, an encapsulant, two circuit patterns and multiple contact vias. The substrate has a top surface, a bottom surface and at least one chip recess. The at least one chip has multiple terminals and is mounted in a corresponding chip recess. The thickness of the chip is equal to or less than the thickness of the substrate. The encapsulant is formed in the chip recess to hold the chip. The circuit patterns are respectively formed on the top and bottom surfaces of the substrate and one of the circuit patterns is connected to the multiple terminals of the chip. The two circuit patterns on two surfaces of the substrate are connected through the multiple contact vias. Therefore, the semiconductor has dual electronic connection faces to be suitable for different applications.Type: ApplicationFiled: June 12, 2004Publication date: December 15, 2005Inventor: Roger Chang