Abstract: Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by e

Abstract: The present invention relates to a voltage control circuit, semiconductor memory device, and method of controlling a voltage in a phase-change memory, wherein the voltage control circuit generates a controlled voltage which can be above the logic supply voltage. This voltage can limit the bit line voltage in a phase-change memory to allow the use of smaller transistors in the memory cells and in the program current part of the circuit. This results in smaller memory cells and modules.

Abstract: The present invention provides a method and device for programming a magnetic random access memory element with reduced current consumption, by re-routing digitline current through a selected bitline in a selected direction.

Abstract: A static memory cell comprising a pair of cross-coupled inverters (10, 12) which is “shadowed” with non-volatile memory elements (14, 16) so that data written in the static memory can be stored in the non-volatile cell, but also can be recalled later. The non-volatile cells (14, 16) are programmed with opposite data to increase the robustness of the retrieval process, and they are cross-coupled to the internal nodes (A, B) of the static memory cell, one the non-volatile cells (14) having a control gate connected to B and its source to A, and the other non-volatile element (16) having a control gate connected to A and its source to B. The drain of each non-volatile element (14, 16) is connected by means of a respective pMOS transistor (18, 20) to a program supply means.

Abstract: Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by e

Abstract: A magnetoresistive memory device comprises magnetoresistive cells, each cell comprising a free magnetic layer and a fixed magnetic layer. The device furthermore comprises a bit line for each magnetoresistive cell and digit lines. Each digit line is common to a number of magnetoresistive cells and is positioned in a direction perpendicular to the bitlines. The magnetic layers are positioned in between the bitlines and the digit lines, but in a reversal of the usual layout according to the prior art, i.e. the digit line is positioned closer to the fixed magnetic layer than to the free magnetic layer. This enables a reduction in total write current where the write current in the line nearer the magnetic layer can be less than the current in a line spaced further away. Since there are more bit lines than digit lines activated, the total of the bit currents and the digit current can be reduced. Reduced total write current is useful in mobile battery powered applications to maximize battery life.

Abstract: An MRAM memory is proposed which gives a maximum read-out signal. This is advantageous for high-speed sensing of the MRAM bits. In an MRAM memory with magnetoresistive memory cells linked together to form logically organized rows and columns, It is obtained by, at least during writing, connecting write bitlines of two adjacent rows or columns with each other, so as to write inverse data values in two adjacent memory cells. In this way, a return path for the writing current is provided in a small loop, which enhances EMC behavior.

Abstract: The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the faulty-address information before it is compared to an externally applied address. Thereby, errors due to faulty redundancy addresses can be prevented.

Abstract: The present invention describes a matrix with magnetoresistive memory cells arranged in logically organized rows and columns, Each memory cell includes a magnetoresistive element. The matrix comprises means for simultaneously reading from one cell in a column and writing to another cell in a column, or means for simultaneous reading from one cell in a row and writing to another cell in the same row. Such matrix can be used in a read-while-write MRAM memory.

Abstract: A static memory cell comprising a pair of cross-coupled inverters (10, 12) which is “shadowed” with non-volatile memory elements (14, 16) so that data written in the static memory can be stored in the non-volatile cell, but also can be recalled later. The non-volatile cells (14, 16) are programmed with opposite data to increase the robustness of the retrieval process, and they are cross-coupled to the internal nodes (A, B) of the static memory cell, one the non-volatile cells (14) having a control gate connected to B and its source to A, and the other non-volatile element (16) having a control gate connected to A and its source to B. The drain of each non-volatile element (14, 16) is connected by means of a respective pMOS transistor (18, 20) to a program supply means.

Abstract: The present invention describes a matrix with magnetoresistive memory cells arranged in logically organized rows and columns, Each memory cell includes a magnetoresistive element. The matrix comprises means for simultaneously reading from one cell in a column and writing to another cell in a column, or means for simultaneous reading from one cell in a row and writing to another cell in the same row. Such matrix can be used in a read-while-write MRAM memory.

Abstract: An MRAM memory is proposed which gives a maximum read-out signal. This is advantageous for high-speed sensing of the MRAM bits. In an MRAM memory with magnetoresistive memory cells linked together to form logically organized rows and columns, It is obtained by, at least during writing, connecting write bitlines of two adjacent rows or columns with each other, so as to write inverse data values in two adjacent memory cells. In this way, a return path for the writing current is provided in a small loop, which enhances EMC behavior.

Abstract: The present invention provides a method and device for programming a magnetic random access memory element with reduced current consumption, by re-routing digitline current through a selected bitline in a selected direction.

Abstract: The present invention relates to electronic memories, more particularly to an improved method and apparatus to read the content of compact 2-transistor flash memory cells. A method of reading a 2-transistor flash memory cell 1 is provided. The memory cell 1 comprises a storage transistor 2 with a storage gate 6 and a selecting transistor 3 with a select gate 7. The method comprises leaving the storage gate 6 floating while the select gate 7 is switched from a first voltage to a second voltage, whereby the first voltage is lower than the second voltage. A device according to the present invention comprises a switching circuit for leaving the storage gate 6 floating while the select gate 7 is switched from the first voltage to the second voltage, the first voltage being lower than the second voltage.

Abstract: The present invention relates to electronic memories, more particularly to an improved method and apparatus to read the content of compact 2-transistor flash memory cells. A method of reading a 2-transistor flash memory cell 1 is provided. The memory cell 1 comprises a storage transistor 2 with a storage gate 6 and a selecting transistor 3 with a select gate 7. The method comprises leaving the storage gate 6 floating while the select gate 7 is switched from a first voltage to a second voltage, whereby the first voltage is lower than the second voltage. A device according to the present invention comprises a switching circuit for leaving the storage gate 6 floating while the select gate 7 is switched from the first voltage to the second voltage, the first voltage being lower than the second voltage.

Abstract: The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the faulty-address information before it is compared to an externally applied address. Thereby, errors due to faulty redundancy addresses can be prevented.

Abstract: The data processing circuit contains a non-volatile memory. Error correction is provided for computing individual correction data for correcting an error in an individual data unit in the non-volatile memory. The individual correction data is computed from a combination of a plurality of data units read from the non-volatile memory. A correction data store stores the individual correction data. Memory access is signaled to the correction data store, which outputs data corrected according to the correction data when said individual data unit is read. The circuit comprises error correction trigger means for triggering the error correction computing means to perform said computing independent of reading of the individual data from the non-volatile memory.

Abstract: The threshold of a number of storage transistors is shifted in steps. After such a step, a collective current through the main current channels of a number of these storage transistors is sensed. The same gate-source voltage is applied to all these transistors during sensing. The collective current indicates whether the threshold of all transistors has been sufficiently shifted. If not, a further threshold shifting step is applied.

Abstract: The invention relates to a non-volatile memory with floating gate, in particular a Flash-EPROM, in which writing takes place through injection of hot electrons into the floating gate and in which erasing takes place through injection of hot holes. To keep the write and erase voltages sufficiently low, p-type zones which locally increase the background doping concentration of the p-type substrate are provided around the n-type source and drain zones. These p-type zones cause an increased field strength at the drain zone whereby hot electrons are formed at the pinch-off point also at lower voltages. This increased background concentration in addition reduces the breakdown voltage of the pn junction of the source and drain zones, so that hot holes for erasing can be formed by pn breakdown at comparatively low voltages. The device is particularly suitable for being integrated into a signal processing IC manufactured in a standard process, such as a microcontroller.

Abstract: The invention relates in particular, though not exclusively, to an integrated circuit with an embedded non-volatile memory with floating gate (10). According to the invention, at least two poly layers of equal or at least substantially equal thickness are used for this device. The first poly layer, poly A, is for the floating gate (10) and for the gates (22) of NMOS and PMOS in the logic portion of the circuit. The second poly layer, poly B, serves exclusively for the control electrode (21) above the floating gate. If so desired, a third poly layer may be deposited for both the control electrode and the logic gates, so that the thicknesses of these electrodes, and thus their resistances, are given desired values. Problems like overetching and bridging during saliciding are prevented in that the control electrode and the logic gates have the same thickness.