Patents by Inventor Roger D. St. Amand
Roger D. St. Amand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11876039Abstract: In one example, a semiconductor device includes a substrate with a top side, a bottom side, and a conductive structure. A first electronic component includes a first side, a second side, and first component terminals adjacent to the first side. The first component terminals face the substrate bottom side and are connected to the conductive structure. A second electronic component comprises a first side, a second side, and second component terminals adjacent to the second electronic component first side. The second electronic component second side is connected to the first electronic component second side with a coupling structure so that the first component terminals and the second component terminals face opposite directions. Interconnects are connected to the conductive structure. The second component terminals and the interconnects are configured for connecting to a next level assembly. Other examples and related methods are also disclosed herein.Type: GrantFiled: June 11, 2022Date of Patent: January 16, 2024Assignee: Amkor Technol Singapore Holding Pte. Ltd.Inventors: Roger D. St. Amand, Louis W. Nicholls
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Patent number: 11621243Abstract: Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.Type: GrantFiled: October 26, 2020Date of Patent: April 4, 2023Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Christopher J. Berry, Roger D. St. Amand, Jin Seong Kim
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Patent number: 11488892Abstract: A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.Type: GrantFiled: July 13, 2020Date of Patent: November 1, 2022Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Louis W. Nicholls, Roger D. St. Amand, Jin Seong Kim, Woon Kab Jung, Sung Jin Yang, Robert F. Darveaux
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Publication number: 20220319969Abstract: In one example, a semiconductor device includes a substrate with a top side, a bottom side, and a conductive structure. A first electronic component includes a first side, a second side, and first component terminals adjacent to the first side. The first component terminals face the substrate bottom side and are connected to the conductive structure. A second electronic component comprises a first side, a second side, and second component terminals adjacent to the second electronic component first side. The second electronic component second side is connected to the first electronic component second side with a coupling structure so that the first component terminals and the second component terminals face opposite directions. Interconnects are connected to the conductive structure. The second component terminals and the interconnects are configured for connecting to a next level assembly. Other examples and related methods are also disclosed herein.Type: ApplicationFiled: June 11, 2022Publication date: October 6, 2022Applicant: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Roger D. ST. AMAND, Louis W. NICHOLLS
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Patent number: 11362027Abstract: In one example, a semiconductor device includes a substrate with a top side, a bottom side, and a conductive structure. A first electronic component includes a first side, a second side, and first component terminals adjacent to the first side. The first component terminals face the substrate bottom side and are connected to the conductive structure. A second electronic component comprises a first side, a second side, and second component terminals adjacent to the second electronic component first side. The second electronic component second side is connected to the first electronic component second side so that the first component terminals and the second component terminals face opposite directions. Substrate interconnects are connected to the conductive structure, and a bottom encapsulant covers the substrate bottom side, the first electronic component, the second electronic component, and the substrate interconnects.Type: GrantFiled: February 28, 2020Date of Patent: June 14, 2022Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Roger D. St. Amand, Louis W. Nicholls
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Publication number: 20210272887Abstract: In one example, a semiconductor device includes a substrate with a top side, a bottom side, and a conductive structure. A first electronic component includes a first side, a second side, and first component terminals adjacent to the first side. The first component terminals face the substrate bottom side and are connected to the conductive structure. A second electronic component comprises a first side, a second side, and second component terminals adjacent to the second electronic component first side. The second electronic component second side is connected to the first electronic component second side so that the first component terminals and the second component terminals face opposite directions. Substrate interconnects are connected to the conductive structure, and a bottom encapsulant covers the substrate bottom side, the first electronic component, the second electronic component, and the substrate interconnects.Type: ApplicationFiled: February 28, 2020Publication date: September 2, 2021Applicant: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Roger D. St. Amand, Louis W. Nicholls
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Publication number: 20210166992Abstract: A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.Type: ApplicationFiled: July 13, 2020Publication date: June 3, 2021Inventors: Louis W. Nicholls, Roger D. St. Amand, Jin Seong Kim, Woon Kab Jung, Sung Jin Yang, Robert F. Darveaux
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Publication number: 20210111151Abstract: Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.Type: ApplicationFiled: October 26, 2020Publication date: April 15, 2021Inventors: Christopher J. Berry, Roger D. St. Amand, Jin Seong Kim
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Patent number: 10818637Abstract: Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.Type: GrantFiled: March 25, 2019Date of Patent: October 27, 2020Assignee: Amkor Technology, Inc.Inventors: Christopher J. Berry, Roger D. St. Amand, Jin Seong Kim
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Patent number: 10714408Abstract: A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.Type: GrantFiled: April 2, 2019Date of Patent: July 14, 2020Assignee: AMKOR TECHNOLOGY, INC.Inventors: Louis W. Nicholls, Roger D. St. Amand, Jin Seong Kim, Woon Kab Jung, Sung Jin Yang, Robert F. Darveaux
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Publication number: 20190371706Abstract: A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.Type: ApplicationFiled: April 2, 2019Publication date: December 5, 2019Inventors: Louis W. Nicholls, Roger D. St. Amand, Jin Seong Kim, Woon Kab Jung, Sung Jin Yang, Robert F. Darveaux
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Publication number: 20190348395Abstract: Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.Type: ApplicationFiled: March 25, 2019Publication date: November 14, 2019Inventors: Christopher J. Berry, Roger D. St. Amand, Jin Seong Kim
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Patent number: 10347562Abstract: A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.Type: GrantFiled: July 28, 2017Date of Patent: July 9, 2019Assignee: Amkor Technology, Inc.Inventors: Louis W. Nicholls, Roger D. St. Amand, Jin Seong Kim, Woon Kab Jung, Sung Jin Yang, Robert F. Darveaux
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Patent number: 10242966Abstract: Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.Type: GrantFiled: July 14, 2017Date of Patent: March 26, 2019Assignee: Amkor Technology, Inc.Inventors: Christopher J. Berry, Roger D. St. Amand, Jin Seong Kim
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Patent number: 9721872Abstract: A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.Type: GrantFiled: February 16, 2012Date of Patent: August 1, 2017Assignee: AMKOR TECHNOLOGY, INC.Inventors: Louis W. Nicholls, Roger D. St. Amand, Jin Seong Kim, Woon Kab Jung, Sung Jin Yang, Robert F. Darveaux
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Patent number: 9711485Abstract: Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.Type: GrantFiled: February 4, 2014Date of Patent: July 18, 2017Assignee: Amkor Technology, Inc.Inventors: Christopher J. Berry, Roger D. St.Amand, Jin Seong Kim
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Patent number: 9496210Abstract: A stackable package is placed within a mold during an encapsulation operation. A compliant surface, e.g., of a compliant film, of the mold is pressed down on upper interconnection balls of the stackable package to force upper portions of the upper interconnection balls into the mold. However, lower portions of the upper interconnection balls are exposed within a space between the compliant surface and a substrate of the stackable package. The space is filled with a dielectric material to form a package body. The package body is formed while at the same time exposing the upper portions of upper interconnection balls from the package body in a single encapsulation operation. By avoiding selective removal of the package body to expose the upper interconnection balls, the number of operations as well as cost to manufacture the stackable package is minimized.Type: GrantFiled: June 7, 2013Date of Patent: November 15, 2016Inventors: Robert Francis Darveaux, Roger D. St. Amand, Vladimir Perelman
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Publication number: 20150221570Abstract: Methods and systems for a thin sandwich embedded package are disclosed and may include bonding a semiconductor die to a first surface of a substrate, dispensing a bond line on the first surface of the substrate and the die, and bonding an interposer to the substrate and die using the dispensed bond line. The bond line may fill the volume between the interposer and the substrate or may fill the volume between the interposer and the die but not between the interposer and the substrate. A cavity structure may be formed on the interposer and/or substrate, wherein the die may be situated within a cavity formed by the cavity structure when the interposer is bonded to the substrate and die. The cavity structure may comprise solder resist. Contacts may be formed on the cavity structure using low volume pad finish metals to electrically couple the interposer to the substrate.Type: ApplicationFiled: February 4, 2014Publication date: August 6, 2015Applicant: Amkor Technology, Inc.Inventors: Christopher J. Berry, Robert Lanzone, Roger D. St.Amand
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Patent number: 8890337Abstract: Stacking balls are formed on ball terminals prior to application of an underfill under a flip chip mounted electronic component. The underfill is then applied and directly contacts and at least partially encloses an inner row of the stacking balls closest to and directly adjacent the flip chip mounted electronic component. By forming the stacking balls prior to the application of the underfill, contamination of the ball terminals by the underfill is avoided. This allows the spacing between the ball terminals and the electronic component to be minimized.Type: GrantFiled: January 10, 2014Date of Patent: November 18, 2014Inventor: Roger D. St. Amand
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Patent number: 8836115Abstract: A stacked inverted flip chip package includes a substrate having a secondary electronic component opening and first traces. Primary flip chip bumps electrically and physically couple a primary electronic component structure to the substrate. Secondary flip chip bumps electrically and physically couple an inverted secondary electronic component to the primary electronic component structure between the primary electronic component structure and the substrate and within the secondary electronic component opening. By placing the secondary electronic component between the primary electronic component structure and the substrate, the height of the stacked inverted flip chip package is minimized.Type: GrantFiled: July 31, 2008Date of Patent: September 16, 2014Inventors: Roger D. St. Amand, August Joseph Miller, Jr., Alexander William Copia, KwangSeok Oh