Abstract: A testing method for a silicon interposer employs a test probe and an electrically conductive glass handler. The silicon interposer includes multiple interconnects that extend between the opposed major surfaces of the interposer, namely from a test side of the interposer to a conductive glass handler side of the interposer. On the glass handler side, the interposer includes a layer of patterned insulative resist with open regions at some interconnects on the glass handler side and remaining resist regions at other interconnects on the glass handler side. The interposer may include a conductive adhesive layer that couples together interconnects at the open regions on the glass handler side. In this manner, a probe may send a test signal from a first interconnect at one location on the test side of the interposer, through the first interconnect, through the conductive adhesive, through a second interconnect to another probe on the test side of the interposer.

Abstract: A testing method for a silicon interposer employs a test probe and an electrically conductive glass handler. The silicon interposer includes multiple interconnects that extend between the opposed major surfaces of the interposer, namely from a test side of the interposer to a conductive glass handler side of the interposer. On the glass handler side, the interposer includes a layer of patterned insulative resist with open regions at some interconnects on the glass handler side and remaining resist regions at other interconnects on the glass handler side. The interposer may include a conductive adhesive layer that couples together interconnects at the open regions on the glass handler side. In this manner, a probe may send a test signal from a first interconnect at one location on the test side of the interposer, through the first interconnect, through the conductive adhesive, through a second interconnect to another probe on the test side of the interposer.

Abstract: Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.

Abstract: The illustrative embodiments described herein provide an apparatus and method for facilitating signal transmission using differential transmission lines. The apparatus includes a first differential transmission line. The first differential transmission line includes a first plurality of conductors. The first plurality of conductors includes a set of conductors. The apparatus also includes a second differential transmission line. The second differential transmission line includes a second plurality of conductors. The second plurality of conductors includes a first conductor and a second conductor. A first noise produced by the first conductor on the set of conductors is balanced by a second noise produced by the second conductor on the set of conductors. The first differential transmission line and the second differential transmission line facilitate signal transmission.

Abstract: The illustrative embodiments described herein provide an apparatus and method for facilitating signal transmission using differential transmission lines. The apparatus includes a first differential transmission line. The first differential transmission line includes a first plurality of conductors. The first plurality of conductors includes a set of conductors. The apparatus also includes a second differential transmission line. The second differential transmission line includes a second plurality of conductors. The second plurality of conductors includes a first conductor and a second conductor. A first noise produced by the first conductor on the set of conductors is balanced by a second noise produced by the second conductor on the set of conductors. The first differential transmission line and the second differential transmission line facilitate signal transmission.

Abstract: Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.

Abstract: Systems and arrangements to assess the thermal performance of a thermal solution based upon the ability of a device under test (DUT) to operate in accordance with electrical performance criteria are contemplated. Embodiments may include a tester to couple with the DUT to determine an operating junction temperature. In some embodiments, the measured junction temperature may be the operating junction temperature anticipated for the DUT in a customer installation. In other embodiments, the tester may comprise logic to calculate a projected, operating junction temperature based upon the measured junction temperature and known differences between the tester and a customer installation. Upon determining the operating junction temperature for the DUT at the customer installation, the operating junction temperature is compared against a maximum junction temperature for proper operation of the DUT. Advantageously, the maximum junction temperature may be varied based upon the project objective for a line of DUTs.

Abstract: A computer implemented method, testing system, computer usable program code, and apparatus are provided for measuring microprocessor susceptibility to internal noise A noise generator modulates a clock signal to generate noise on a targeted component within a microprocessor. A function generator executes microprocessor functions on a plurality of functional components within the microprocessor. A maximum execution frequency on the plurality of functional components is then measured and a set of frequency ranges where the functional components are susceptible to the generated noise is determined.

Abstract: A spread spectrum clock system (11) modulates the supply voltage for a circuit (10) in concert with the circuit clock frequency (C). The system increases the supply voltage for the circuit (10) in phase with increases in the circuit clock frequency (C). However, in the portion of the clock frequency modulation period in which the clock frequency (C) is decreasing, the system (11) also decreases the supply voltage for the circuit (10). This relationship between the circuit supply voltage and circuit clock frequency (C) may be accomplished by modulating the output (18) of a power supply (15) for the circuit (10) and applying that modulated supply voltage signal through a signal translator (30) to control modulation of a clock source (14).