Abstract: Circuits, methods, and apparatus for reordering memory access requests in a manner that reduces the number of page misses and thus increases effective memory bandwidth. An exemplary embodiment of the present invention uses an exposed FIFO structure. This FIFO is an n-stage bubble compressing FIFO that preserves the order of requests but allows bypassing to avoid page misses and their resulting delays. A specific embodiment exploits DRAM page locality by maintaining a set of history registers that track the last bank and row usage. Embodiments of the present invention may limit the number of times a request may be bypassed by incrementing an associated bypass counter each time the request is bypassed. Further, to avoid continuous page misses that may occur if requests alternate between two rows, a hold-off counter may be implemented.

Abstract: A method of accessing common memory in a cluster architecture for a highly parallel multiprocessor scaler/factor computer system using a plurality of segment registers in which is first determined whether a logical address is within a start and end range as defined by the segment registers and then relocating the logical address to a physical address using a displacement value in another segment register.

Abstract: A method and apparatus for providing a resource lockout mechanism in a shared memory, multiprocessor system that is capable of performing both a read and write operation during the same memory operation. The load and flag instruction of the present invention can execute a read operation, followed by a write operation of a preselected flag value to the same memory location during the same memory operation. The load and flag instruction is particularly useful as a resource lockout mechanism for use in Monte Carlo applications.

Abstract: The present invention provides a method and apparatus for handling memory hazards in processors having multiple memory ports wherein the operation of marking of the memory requests that may be related to a memory hazard is separated from the operation of waiting for the memory hazard to clear. The separation of the operation of marking of memory hazards from the operation of waiting for memory hazards to clear allows a compiler to schedule other instructions, as well as other memory operations not directed to the memory location involved in the memory hazard sequence, during the time between the operations of marking and waiting for the memory hazard to clear. The waiting period ends once it is clear that the marked memory requests will execute in the order in which they were issued.

Abstract: A method and apparatus for non-sequential access to shared resources in a multiple requestor system uses a variety of tags to effectively re-order the data at its destination. In simplest form, the tag directs switching logic to where in a buffer to locate another tag for direction information or where in a buffer or processor (register) to put the response associated with the tag. For example, loading data from memory requires that the requestor provide a request signal, an address, and a request tag. The request signal validates the address and request tag. The address specifies the location of the requested data in memory. The request tag specifies where to put the data when it is returned to the processor.

Abstract: A cluster architecture for a highly parallel multiprocessor computer processing system is comprised of one or more clusters of tightly-coupled, high-speed processors capable of both vector and scalar parallel processing that can symmetrically access shared resources associated with the cluster, as well as the shared resources associated with other clusters.

Abstract: A multiple request toggling (MRT) arbitration system for prioritizing requests to a set of shared resources by multiple requestors, especially requests by multiple processors to shared resources in a multiprocessor system. The MRT arbitration system assigns priority to multiple requests on a first-come, first-serve basis with the priority of multiple simultaneous requests being resolved through an arbitration network.