Abstract: An external time source is connected to a partitioned data processing system, having host processors controlled by a host hypervisor, and having operating systems in the partitions. The host processors each have a timer facility comprising a time-of-day (TOD) clock, and a clock comparator. When the hypervisor detects a need for synchronization between the external time source and a host timer facility, it insulates the operating system in the partition on that host from host synchronization, and synchronizes the host timer facility with the external time source. Subsequently, the operating system is placed into normal execution, with an adjustment value used for timer facility references, and with a synchronization interrupt pending if the operating system is aware of the external time source.

Abstract: Enables any OS of plural OSs within any of plural logical-resource partitions (LPARs) of a CEC to use interpretive execution for synchronously-executable CHSC (channel subsystem call) commands. A CHSC command authorization mask (CCAM) is provided to control which CHSC commands are allowed to execute interpretively (with pass-through), and which commands are executed with hypervisor intervention (as all prior CHSC commands did). By enabling interpretive execution of those commands which can successfully operate with pass-through, significant system efficiency is obtained. And by disabling interpretive execution for a subset of CHSC commands (which are not allowed to execute with pass-through) potential system failures may be prevented. Thus, interpretive execution may be restricted differently among the OSs in a CEC. Novel CHSC command execution now handles multiple images of shared I/O resources by use of image identifiers, which could not be done before.

Abstract: A data processing system operating under a multiprocessing hypervisor program subject to I/O interrupts during a polling interval of the hypervisor program includes one or more processors for executing the hypervisor program and host system and one or more guest systems under the hypervisor program, a storage system connected to the processor's by a bus for storing instructions, data and control information associated with the systems being executed by the processor, the storage system may be partitioned into a number of separate areas each associated with one of the concurrently operating systems, an input/output subsystem for generating I/O interrupts to the processors, apparatus for testing to determine if the system is operating in an interpretive execution mode, apparatus for determining whether a dedicated region facility is active, apparatus for testing whether an I/O enablement mask for a guest system has been set, apparatus for setting a flag if the guest system I/O enablement mask is set, apparatus

Abstract: This invention involves reconfiguration support for shared I/O resources in a a computer electronic complex (CEC) supporting both shared and unshared I/O channels of the type described and claimed in U.S. patent application Ser. No. 07/898,867 (PO9-92-016) filed on the same day as the subject application and assigned to the same assignee as the subject application. Prior channel subsystem call (CHSC) instructions cannot execute when a channel is to be configured as shareable by plural operating systems in a CEC.

Abstract: Provides a method for increasing the connectivity of I/O resources to a multiplicity of operating systems (OSs) running in different resource partitions of a computer electronic complex (CEC) to obtain sharing of the I/O resources among the OSs of the CEC, including channels, subchannels (devices), and control units (CUs). The invention provides image identifiers (IIDs) for assigning resources to the different OSs. Each shared I/O resource has a sharing set of control blocks (CBs) in which a respective CB is assigned to (and located by) a respective IID of one of the OSs. Each of the CBs in a sharing set provides a different image of the same I/O resource. The different CB images are independently set to different states by I/O operations for the different OSs, so that the OSs can independently share the same I/O resource.

Abstract: A system and method for dispatching logical central processing units (CPUs) among physical CPUs in a multiprocessor computer system having multiple logical partitions, wherein the cryptographic facilities may not be interchangeable. According to the present invention, the logical CPUs are dispatched among the physical CPUs according to either an affinity, floating, or disabled scheduling method. The affinity scheduling method is used when the crypto facilities are not interchangeable or when non-interchangeable crypto functions are performed. The floating scheduling method is used when the cryptographic facilities are interchangeable and interchangeable crypto functions are performed. The disabled scheduling method is used when the logical CPU is not authorized to issue cryptographic instructions.

Abstract: A data processing system operated with multiple levels of virtual machine guests under a host control program. The second level of guests are invoked, operated, and terminated without host intervention, as has been required in prior systems, to significantly increase the operating efficiency of the system. Address translation is done by providing machine capability to translate second level guest addresses to real memory addresses taking advantage of the first level guest being located at a simple offset within real memory. Special facilities for second level guests periodically test for timing interruptions for second level guests and update the second level guest timing facilities.

Abstract: Enables a host (hypervisor) to access any location in any guest zone in a large memory, when host and guest operands have small addresses that cannot access locations outside of their own zones. System hardware/microcode provides a particular number of windows for host use. Each CPU in the system has one or more window access registers (WARs), and one or more window registers (WRs). The host uses a load WAR instruction to designate each page frame (PF) in the host zone to be used as a host window, and each PF is associated with a respective window number. When the host receives an interception signal requiring the host to access a guest location represented by a guest zone identifier and a guest small address, the host designates one of its window numbers for an access to this guest location.

Abstract: A technique, specifically apparatus and an accompanying method, for use in, e.g., a "host" operating system (610), for properly updating a dynamically alterable channel program that controls an input/output (I/O) device so as to emulate a "guest" computer system, that employs dynamic address translation (DAT) in an I/O channel sub-system (150), on a "host" computer system (10) that does not. This technique performs this updating in a manner that significantly increases channel throughput so as to substantially reduce a performance degradation that would otherwise result from a lack of channel DAT on the host system. Specifically, our technique relies on program controlled interrupt (PCI) chaining coupled with use of "just-in-time" translation of each new virtual channel program segment generated by a guest operating system (620) and corresponding updating of channel program (415) then executing on the host computer system.

Abstract: A system for reducing purging of a translation lookaside buffer (TLB) to reduce operating system overhead in a system running multiple levels of virtual machines. A system typically must purge TLB entries whenever an underlying page table entry is invalidated due to paging activity on the host machine, or an underlying guest machine. A system for reducing the number of cases in which guest translations are based on host page table entries is provided. Additional logic is supplied to analyze each invalidate page table entry (IPTE) instruction to minimize the extent of purging required as a result of that instruction. When the region relocate facility is in operation, or when no pageable TLB's have been constructed, only the entry corresponding to the page table entry to be invalidated need be purged. This limited purging reduces the overhead by reducing the time spent in purging and the time required in address translation to rebuild the TLB.

Abstract: A tightly-coupled processor complex comprises two or more processors, the complex being asymmetric in that a feature available on one processor is not available on at least one other processor. A work selection mechanism selects one of a set of one or more ready work units, each capable of execution on one or more of the asymmetric processors. A processor set identification function identifies an "indirect idle" set of processors which can participate as hosts in work reassignment to make use of a previously idle processor, and identifies an "indirect bump" set of processors which can participate as hosts in work reassignment to displace a lowest priority work unit previously executing - any work reassignment being initiated by an assigner means and comprising an optimized number of work reassignment steps reassigning work among one of the processor sets to accomplish a related assignment goal (making use of a previously idle processor, or displacing a lowest priority work unit).

Abstract: A request is made by a system in a first logical partition, within a logically partitioned data processing system, to dynamically change the I/O configuration of the host system in a way that affects a system in a second logical partition. The hypervisor intercepts the request, ensures the serialization of such dynamic I/O requests, and allows dynamic reconfiguration to proceed. Subsequently, the hypervisor determines the effect of the reconfiguration on the second partition, and notifies the second partition of the change.

Abstract: A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.

Abstract: The embodiment discloses a method and means for partitioning the resources in a data processing system into a plurality of logical partitions. Host control code may be embodied in programming, microcode, or by special hardware to enable highly efficient operation of a plurality of preferred guest programming systems in the different partitions of the system. The main storage, expanded storage, the channel, and subchannel resources of a system are assigned to the different logical partitions in the system to enable a plurality of preferred guest programming systems to run simultaneously in the different partitions. This invention automatically relocates the absolute addresses of the I/O channel and subchannel resources in the system to their assigned partitions. Also the absolute and virtual addresses of the different guest programming systems are relocated into, as well as page addresses for any expanded storage, their assigned partitions.

Abstract: The embodiments enable address translations for a virtual machine in the TLB (translation lookaside buffer) of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation of guest TLB entries on entry to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest in a virtual multi-processor (MP) machine, an interlock is provided to allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity.

Abstract: A method for controlling both shared and exclusive access for a resource in a multiprocessor system wherein a first-in/first-out queue is formed for tasks suspended while awaiting access and wherein access to the resource provides that control of access required for manipulation of the first-in/first-out queue which is not provided by the atomic nature of compare (double) and swap. Each member of the queue has indicators of the access it requested and of the next most recently enqueued member which has a corresponding indicator. A lockword is established having two parts, a lock flag indicating the status of the resource, whether available, under shared ownership or under exclusive ownership and a lock pointer pointing to the most recently enqueued task. In requesting or releasing access, an initial guess is made as to the value of the lockword and a projected lockword is calculated based on the guess.