Patents by Inventor Roger Espasa
Roger Espasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170308383Abstract: A method in a processor includes receiving an instruction indicating a first source packed data operand having a first plurality of data elements each having a plurality of bit groups, and indicating a second source packed data operand having a second plurality of data elements each having a plurality of bit groups. Each data element of the first plurality corresponding to a different data element of the second plurality in a corresponding position. Each bit group in each data element of the first plurality corresponding to a different hit group in a corresponding position in a corresponding data element of the second plurality. Storing a result packed data operand in a destination storage location in response to the instruction. The result packed data operand including every other bit group of the first source packed data operand interleaved with every other corresponding bit group of the second source operand.Type: ApplicationFiled: September 4, 2015Publication date: October 26, 2017Applicant: Intel CorporationInventors: Roger Espasa, David Guillen Fandos, Guillem Sole
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Patent number: 9785433Abstract: A processor includes a decode unit to decode a three source floating point addition instruction indicating a first source operand having a first floating point data element, a second source operand having a second floating point data element, and a third source operand having a third floating point data element. An execution unit is coupled with the decode unit. The execution unit, in response to the instruction, stores a result in a destination operand indicated by the instruction. The result includes a result floating point data element that includes a first floating point rounded sum. The first floating point rounded sum represents an additive combination of a second floating point rounded sum and the third floating point data element. The second floating point rounded sum represents an additive combination of the first floating point data element and the second floating point data element.Type: GrantFiled: March 12, 2015Date of Patent: October 10, 2017Assignee: Intel CorporationInventors: Roger Espasa, Guillem Sole, Manel Fernandez
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Publication number: 20170286112Abstract: A processor includes packed data registers and a decode unit to decode an instruction. The instruction is to indicate a first source operand having at least one lane of bits, and a second source packed data operand having a number of sub-lane sized bit selection elements. An execution unit is coupled with the packed data registers and the decode unit. The execution unit, in response to the instruction, stores a result operand in a destination storage location. The result operand includes, a different corresponding bit for each of the number of sub-lane sized bit selection elements. A value of each bit of the result operand corresponding to a sub-lane sized bit selection element is that of a bit of a corresponding lane of bits, of the at least one lane of bits of the first source operand, which is indicated by the corresponding sub-lane sized bit selection element.Type: ApplicationFiled: September 4, 2015Publication date: October 5, 2017Applicant: Intel CorporationInventors: Roger Espasa, Guillem Sole, David Guillen Fandos
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Patent number: 9733935Abstract: A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second operand source address identifies a location of a second mask pattern in the mask register space. The method further includes fetching the first mask pattern from the mask register space; fetching the second mask pattern from the mask register space; merging the first and second mask patterns into a merged mask pattern; and, storing the merged mask pattern at a storage location identified by the destination address.Type: GrantFiled: December 23, 2011Date of Patent: August 15, 2017Assignee: Intel CorporationInventors: Jesus Corbal, Andrew T. Forsyth, Roger Espasa, Manel Fernandez, Thomas D. Fletcher
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Publication number: 20170199825Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.Type: ApplicationFiled: December 19, 2016Publication date: July 13, 2017Inventors: Edward Grochowski, Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa
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Publication number: 20170192904Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.Type: ApplicationFiled: December 19, 2016Publication date: July 6, 2017Inventors: Edward Grochowski, Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa
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Patent number: 9654143Abstract: Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values.Type: GrantFiled: June 18, 2014Date of Patent: May 16, 2017Assignee: Intel CorporationInventors: Guillem Sole, Roger Espasa, Sorin Iacobovici, Brian Hickmann, Wei Wu, Thomas Fletcher
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Patent number: 9606931Abstract: Some implementations disclosed herein provide techniques and arrangements for indicating a length of an instruction from an instruction set that has variable length instructions. A plurality of bytes that include an instruction may be read from an instruction cache based on a logical instruction pointer. A determination is made whether a first byte of the plurality of bytes identifies a length of the instruction. In response to detecting that the first byte of the plurality of bytes identifies the length of the instruction, the instruction is read from the plurality of bytes based on the length of the instruction.Type: GrantFiled: December 29, 2011Date of Patent: March 28, 2017Assignee: Intel CorporationInventors: Santiago Galan, Roger Espasa, Julio Gago, Jose Gonzalez
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Patent number: 9513917Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.Type: GrantFiled: January 31, 2014Date of Patent: December 6, 2016Assignee: Intel CorporationInventors: Robert C. Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert D. Cavin, Bret L. Toll, Santiago Galan Duran, Jeffrey G. Wiedemeier, Sridhar Samudrala, Milind Baburao Girkar, Edward Thomas Grochowski, Jonathan Cannon Hall, Dennis R. Bradford, Elmoustapha Ould-Ahmed-Vall, James C. Abel, Mark Charney, Seth Abraham, Suleyman Sair, Andrew Thomas Forsyth, Lisa Wu, Charles Yount
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Publication number: 20160283242Abstract: An apparatus and method are described for performing vector horizontal logical instruction. For example, one embodiment of a processor comprises: fetch logic to fetch an instruction from memory, and execution logic to determine a value of a first set of one or more data elements from a first specified set of bits of an immediate operand, wherein positions of the first set of one or more data elements determined from the first specified set of bits of the immediate operand are based on a first set of one or more index values that have a most significant bit corresponding to a packed data element at a first set of one or more positions of a destination packed data operand and that have a least significant bit corresponding to a data element at a corresponding position of a first source packed data operand.Type: ApplicationFiled: December 23, 2014Publication date: September 29, 2016Inventors: Elmoustapha OULD-AHMED-VALL, David GUILLEN FANDOS, Jesus F. SANCHEZ, Guillem SOLE, Roger ESPASA
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Patent number: 9436468Abstract: A technique to generate a vector mask. In particular, at least one embodiment of the invention matches at least two instructions used in generating a vector mask and prevents at least one of the two instructions from executing if the correlation is found.Type: GrantFiled: November 22, 2005Date of Patent: September 6, 2016Assignee: Intel CorporationInventors: Roger Espasa, Roger Gramunt
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Publication number: 20160188333Abstract: An apparatus and method for mask compression. For example, one embodiment of a processor comprises: a source mask register to store a plurality of mask bits including a plurality of set bits and a plurality of bits that are not set; a destination mask register to store set bits read from the source mask register; and mask compression logic to read each of the set bits from the source mask register and to store the set bits in contiguous bit locations on one side of the destination mask register.Type: ApplicationFiled: December 27, 2014Publication date: June 30, 2016Inventors: ELMOUSTAPHA OULD-AHMED-VALL, ROBERT VALENTINE, JESUS CORBAL SAN ADRIAN, BRETT L. TOLL, MILIND B. GIRKAR, MARK J. CHARNEY, GUILLEM SOLE, ROGER ESPASA
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Publication number: 20160188327Abstract: In one embodiment of the invention, a processor device including a storage location configured to store a set of source packed-data operands, each of the operands having a plurality of packed-data elements that are positive or negative according to an immediate bit value within one of the operands. The processor also including: a decoder to decode an instruction requiring an input of a plurality of source operands, and an execution unit to receive the decoded instructions and to generate a result that is a product of the source operands. In one embodiment, the result is stored back into one of the source operands or the result is stored into an operand that is independent of the source operands.Type: ApplicationFiled: December 24, 2014Publication date: June 30, 2016Inventors: Elmoustapha OULD-AHMED-VALL, Robert VALENTINE, Jesus CORBAL, Mark CHARNEY, Roger ESPASA, Guillem SOLE, Manel FERNANDEZ, Brian J. HICKMANN
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Publication number: 20160188341Abstract: In one embodiment of the invention, a processor including a storage location configured to store a set of source packed-data operands, each of the operands having a plurality of packed-data elements that are positive or negative according to an immediate bit value within one of the operands. The processor also including: a decoder to decode an instruction requiring an input of a plurality of source operands, and an execution unit to receive the decoded instructions and to generate a result that is a sum of the source operands. In one embodiment, the result is stored back into one of the source operands or the result is stored into an operand that is independent of the source operands.Type: ApplicationFiled: December 24, 2014Publication date: June 30, 2016Inventors: Elmoustapha OULD-AHMED-VALL, Robert Valentine, Jesus Corbal, Mark Charney, Roger Espasa, Guillem Sole, Manel Fernandez, Brian J. Hickmann
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Publication number: 20160188335Abstract: An apparatus and method for performing a vector bit gather. For example, one embodiment of a processor comprises: a first vector register to store one or more source data elements; a second vector register to store one or more control elements, each of the control elements comprising a plurality of bit fields, each bit field to be associated with a corresponding bit position in a destination vector register and to identify a bit from the one or more source data elements to be copied to each of the particular bit positions; and vector bit gather logic to read each bit field from the second vector register to identify a bit from the one or more source data elements and to responsively copy the bit from each of the one or more source data elements to each of the corresponding bit positions in the destination vector register.Type: ApplicationFiled: December 27, 2014Publication date: June 30, 2016Inventors: ELMOUSTAPHA OULD-AHMED-VALL, ROBERT VALENTINE, JESUS CORBAL SAN ADRIAN, MARK J. CHARNEY, GUILLEM SOLE, ROGER ESPASA
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Publication number: 20160188530Abstract: An apparatus and method for performing a vector permute.Type: ApplicationFiled: December 27, 2014Publication date: June 30, 2016Inventors: JESUS CORBAL SAN ADRIAN, ELMOUSTAPHA OULD-AHMED-VALL, ROBERT VALENTINE, MARK J. CHARNEY, MILIND B. GIRKAR, BRET L. TOLL, ROGER ESPASA, GUILLEM SOLE, JAIRO BALART, BRIAN HICKMAN
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Publication number: 20160188532Abstract: An apparatus and method for performing a vector bit shuffle. For example, one embodiment of a processor comprises: a first vector register to store a plurality of source data elements; a second vector register to store a plurality of control elements, each of the control elements comprising a plurality of bit fields, each bit field to be associated with a corresponding bit position in a destination mask register and to identify a bit from each of the source data elements to be copied to each of the particular bit positions; and vector bit shuffle logic to read each bit field from the second vector register to identify a bit from each of the source data elements and to responsively copy the bit from each of the source data elements to each of the corresponding bit positions in the destination mask register.Type: ApplicationFiled: December 27, 2014Publication date: June 30, 2016Inventors: ELMOUSTAPHA OULD-AHMED-VALL, JESUS CORBAL SAN ADRIAN, ROBERT VALENTINE, MARK J. CHARNEY, GUILLEM SOLE, ROGER ESPASA
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Publication number: 20160179523Abstract: An apparatus and method are described for performing a vector broadcast and XORAND logical instruction. For example, one embodiment of a processor comprises: fetch logic to fetch an instruction from memory indicating a destination packed data operand, a first source packed data operand, a second source packed data operand, and an immediate operand, and execution logic to determine a bit in the second source packed data operand based a position corresponding to the immediate value, perform a bitwise AND between the first source packed data operand and the determined bit to generate an intermediate result, perform a bitwise XOR between the destination packed data operand and the intermediate result to generate a final result, and store the final result in a storage location indicated by the destination packed data operand.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: Elmoustapha OULD-AHMED-VALL, David GUILLEN FANDOS, Jesus F. SANCHEZ, Guillem SOLE, Roger ESPASA
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Patent number: 9244855Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.Type: GrantFiled: December 31, 2007Date of Patent: January 26, 2016Assignee: Intel CorporationInventors: Ed Grochowski, Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa
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Publication number: 20150370636Abstract: Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values.Type: ApplicationFiled: June 18, 2014Publication date: December 24, 2015Inventors: Guillem Sole, Roger Espasa, Sorin Iacobovici, Brian Hickmann, Wei Wu, Thomas Fletcher