Abstract: The invention reduces the effects of stitching errors from re-scaling or re-positioning in the fabrication of fiber Bragg gratings or the mask used in such fabrication. A first embodiment of the invention preferably uses characteristics of stitching errors to compensate for the stitching errors themselves. By increasing the number of stitching errors, errors caused by the stitching errors can be reduced. A second embodiment uses continuous writing of the desired pattern, wherein the desired pattern is snapped to a grid that can be written by the fabrication equipment. Using continuous writing eliminates stitching errors in the resulting gratings.

Abstract: The invention reduces the effects of stitching errors from re-scaling or re-positioning in the fabrication of fiber Bragg gratings or the mask used in such fabrication. A first embodiment of the invention preferably uses characteristics of stitching errors to compensate for the stitching errors themselves. By increasing the number of stitching errors, errors caused by the stitching errors can be reduced. A second embodiment uses continuous writing of the desired pattern, wherein the desired pattern is snapped to a grid that can be written by the fabrication equipment. Using continuous writing eliminates stitching errors in the resulting gratings.

Abstract: A method for forming a gap in a silicon layer is described. A silicon layer is formed over a substrate. A nitride layer is formed over the silicon layer and an oxide layer is formed over the silicon layer, adjacent to the nitride layer. A portion of the oxide layer is then removed to form an exposed region of the silicon layer. Then an etchant is applied to the exposed region to form an gap of the silicon layer.

Abstract: A method for forming an alignment mark during semiconductor device manufacturing. A first area and a second area are provided on the semiconductor substrate wherein the second area is adjacent to the first area. An alignment mark is formed in the first area. A first layer is formed over the first area and the second area wherein the alignment mark is replicated in the first layer. The first layer is then removed from the second area and left over the first area. A globally planarized second layer, is formed over the first area and the second area. The second layer is then removed from the first area and is left over the second area.

Abstract: A method for forming an alignment mark during semiconductor device manufacturing. A first alignment mark having a first step height is formed in a semiconductor substrate. An interlayer dielectric is formed over the alignment mark and planarized to a first thickness. During contact/via etch an opening is formed through the first dielectric layer away from the first alignment mark. The opening is then filled with a material until the material in the bottom of the opening has a thickness less than thickness of the planarized dielectric layer.

Abstract: A method for forming an alignment mark during semiconductor device manufacturing. A first area and a second area are provided on the semiconductor substrate wherein the second area is adjacent to the first area. An alignment mark is formed in the first area. A first layer is formed over the first area and the second area wherein the alignment mark is replicated in the first layer. The first layer is then removed from the second area and left over the first area. A globally planarized second layer, is formed over the first area and the second area. The second layer is then removed from the first area and is left over the second area.