Abstract: A processor suitable for recursive computations is arranged to multiply successive input data words by a co-efficient word to produce results. It incorporates multiplier cells connected to form rows and columns. Each row is arranged to multiply a respective input data digit by the co-efficient. It begins with accumulator cells and continues with multiplier cells each arranged to multiply by an individual co-efficient digit and disposed in the row in descending order of digit significance. Columns other than the first column begin with a multiplier cell, and the higher significance columns terminate at respective accumulator cells. Any intervening multiplier cells are arranged in ascending order of multiplier digit significance. The processor employs radix 2 arithmetic. Each accumulator cell employs redundant radix 2 arithmetic, and each adds the highest significance transfer digit output of its row to at least three digits of equal and higher significance output from a preceding row.

Abstract: A wave digital filter implements a pipelining strategy to significantly increase the processing speed of circuits. The implementation allows high frequency digital signals to be processed at higher speeds than were previously possible. The implementation overcomes potential hardware limitation of wave digital filters and allows pipelining to be applied without introducing delays into the feedback loops. In particular, the implementation teaches how to increase the processing speed of a two port adaptor which is commonly used in the construction of wave digital filters.