Abstract: This invention teaches an apparatus and method for determining a more efficient quality assurance or reliability test screen without falsely rejecting, i.e., over stressing, short channel length devices during voltage stress test screening. Short channel lengths devices fabricated on a semiconductor wafer have a higher tendency to fail at voltage levels that would otherwise not harm long channel length devices. The failures, however, are not related to device defects. Protection to the more vulnerable devices is provided by determining the speed of the die prior to the voltage test screen, thus, segregating the devices based on operational speed performance. Next, a lower voltage is effectively applied during wafer probe test to the faster devices, which directly correspond to the population of short channel devices. A preferred measurement for device speed entails measuring the drain-to-source current of each FET, and dividing the resultant sum by the device gate channel width.

Abstract: This invention teaches an apparatus and method for determining a more efficient quality assurance or reliability test screen without falsely rejecting, i.e., over stressing, short channel length devices during voltage stress test screening. Short channel lengths devices fabricated on a semiconductor wafer have a higher tendency to fail at voltage levels that would otherwise not harm long channel length devices. The failures, however, are not related to device defects. Protection to the more vulnerable devices is provided by determining the speed of the die prior to the voltage test screen, thus, segregating the devices based on operational speed performance. Next, a lower voltage is effectively applied during wafer probe test to the faster devices, which directly correspond to the population of short channel devices. A preferred measurement for device speed entails measuring the drain-to-source current of each FET, and dividing the resultant sum by the device gate channel width.