Abstract: A method, system and apparatus for testing an integrated circuit chip. The system including: means for forming a liquid polyalphaolefine layer on a bottom surface of the integrated circuit chip, a top surface of the integrated circuit chip having and a bottom surface not having signal and power pads; means for placing a surface of a heat sink into physical contact with the bottom surface of the polyalphaolefine layer; means for electrically coupling the integrated circuit chip to a tester; means for electrically testing the integrated circuit chip; means for electrically de-coupling the integrated circuit chip from the tester; means for removing the heat sink from contact with the polyalphaolefine layer, all or a portion of the polyalphaolefine layer remaining on the bottom surface of the integrated circuit chip; and means for removing the polyalphaolefine layer from the bottom surface of the integrated circuit chip.

Abstract: A method, system and apparatus for testing an electronic device. The method including: (a) forming a temporary liquid heat transfer layer on a surface of the electronic device; after step (a), (b) placing a surface of a heat sink into physical contact with a surface of the heat transfer layer; after step (b), (c) electrically testing the electronic device; after step (c), (d) removing the heat sink from contact with the heat transfer layer; and after step (d), (e) removing any heat transfer layer remaining on the electronic device from the surface of the electronic device.

Abstract: An improved method of burn-in of I/C chips is provided wherein, at the beginning of the burn-in process, the thermal resistance between the heatsink and the chip is measured at reduced power, the maximum allowable thermal resistance between the chip and heatsink interface is calculated and compared to the actual thermal resistance of the interface. If the actual thermal resistance measured at the interface between the heatsink and the chip package is greater than the maximum allowable calculated thermal resistance, then the corrective action is initiated in order to prevent damage to the I/C chip during burn-in or increase efficient use of the test sites.

Abstract: An improved method of burn-in of I/C chips is provided wherein, at the beginning of the burn-in process, the thermal resistance between the heatsink and the chip is measured at reduced power, the maximum allowable thermal resistance between the chip and heatsink interface is calculated and compared to the actual thermal resistance of the interface. If the actual thermal resistance measured at the interface between the heatsink and the chip package is greater than the maximum allowable calculated thermal resistance, then the corrective action is initiated in order to prevent damage to the I/C chip during burn-in or increase efficient use of the test sites.