Abstract: The present invention is a method and apparatus for transferring data from at least two source operands to a destination operand based on a condition. The two source operands are stored in respective source registers. A condition register stores a condition operand from the condition. A masking circuit is coupled to the two source registers for masking the two source operands by the condition operand to generate a masking result. A selector is coupled to the masking circuit for selecting elements of the two source operands based of the masking result.

Abstract: A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.

Abstract: A system for processing SIMD operands in a packed data format includes a scalar FMAC and a vector FMAC coupled to a register file through an operand delivery module. For vector operations, the operand delivery module bit steers a SIMD operand of the packed operand into an unpacked operand for processing by the first execution unit. Another SIMD operand is processed by the vector execution unit.

Abstract: A method and apparatus for performing complex arithmetic is disclosed. In one embodiment, a method comprises decoding a single instruction, and in response to decoding the single instruction, moving a first operand occupying lower order bits of a first storage area to higher order bits of a result, moving a second operand occupying higher order bits of a second storage area to lower order bits of the result, and negating one of the first and second operands of the result.

Abstract: An apparatus, a processor, a computer system and a method may be used to directly transfer and translate data between a memory format in an integer processing unit and a floating point format in a floating point processing unit. Data is stored in integer registers of the integer processing unit in a memory format and is stored in floating point registers of the floating point processing unit in a floating point format. A direct data link is provided between the integer register file of the integer processing unit and the floating point register file of the floating point processing unit. The direct data link includes a logic circuit which translates data between the memory format and the floating point format.

Abstract: A computer program product and method for multiplying a sparse matrix by a vector are disclosed. The computer program product includes a computer readable medium for storing instructions, which, when executed by a computer, cause the computer to efficiently multiply a sparse matrix by a vector, and produce a resulting vector. The computer is made to create a first array containing the non-zero elements of the sparse matrix, and a second array containing the end_of_row position of the last non-zero element in each row of the sparse matrix. A variable is initialized, and then, for each row of the second array, the computer is made to do one of two things. Either, it equates the variable to the sum of the variable and the product of a particular element of the first array and a particular element of the vector. Or, it equates a particular element of the resulting vector to the variable, and then equates the variable to a particular value.

Abstract: A method and apparatus for converting a packed integer data item having first and second data elements, to a packed floating-point data item. In one embodiment, a method includes moving the first data element of the integer data item to a first data element of a first intermediate data item and extending a sign of the first data element into all bit positions of a second data element of the first intermediate data item. The method further includes moving the second data element of the integer data item to a first data element of a second intermediate data item and extending a sign of the second data element into all bit positions of a second data element of the second intermediate data item. The first and second intermediate data items are converted from integer data items to respective floating-point data items, and the first and second intermediate floating-point data items are packed to first and second data elements of a result.

Abstract: A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Abstract: A method and apparatus for reducing the number of opcodes required in a computer architecture using an operation class code and an operation selector code. A processor contains a fetch unit which fetches instructions to be executed by the processor. An instruction may conform to an instruction format which includes a number of fields that specify an operation class code, an operation selector code, and one or more operands. The processor also contains a decoder which uses the operation class code to generate a single execution flow that is capable of executing a class of similar operations. The single execution flow, in the form of execution control information, is sent to an execution unit along with the associated operands. The operation selector code is also passed to the execution unit. The execution unit performs the specific operation identified by the operation selector code and execution control information.

Abstract: A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Abstract: An apparatus to improve the speed of handling of denormal numbers in a computer system, the apparatus comprising a mode bit and a selector, the mode bit set when denormals are to be replaced by zero, the selector having a first input and an output, the first input comprising a floating point number, the selector selecting zero to become the output when the floating point number is denormal and the mode bit is set, the selector selecting the floating point number to become the output otherwise.

Abstract: The present invention discloses a method and apparatus for synchronizing weakly ordered write combining operations. A memory controller has a buffer to service memory accesses. A store fence instruction is dispatched to the memory controller. If the buffer contains at least a data written by at least one of the weakly ordered write combining operations prior to the store fence instruction, then the store fence instruction is blocked until a block in the buffer containing the data is globally observed. If the buffer does not contain any data written by at least one of the write combining operations prior to the store fence instruction, then the store fence instruction is accepted by the memory controller.

Abstract: An emulating agent and method is provided that receives numbers having si, exponents and significands of varying lengths and possibly configured in a variety of incompatible formats and to reformat the numbers into a standard uniform format for uniform arithmetic computations in processors operating with different architectures. In one embodiment, the emulating agent has a three-field superset register configured to receive the sign of a number in a first field, the exponent of a number in a second field and the significand of a number in a third field, regardless of the original format of the number, resulting in a number represented in a standard uniform format for computation. The embodiment also allows high level access to the fields to allow users to control the size of the numbers inserted into the fields.

Abstract: A method and apparatus for controlling groups of registers includes a pluity of registers of the same type logically separated into a plurality of groups and a plurality of indicators corresponding to the plurality of groups of registers, each of the plurality of indicators identifying whether a corresponding group of registers has been modified by a task currently being executed by the processor. A control logic is also included, coupled to the plurality of registers, to selectively control the plurality of registers by group based at least in part on the plurality of indicators.

Abstract: An apparatus to improve the speed of handling of denormal numbers in a computer system, the apparatus comprising a mode bit and a selector, the mode bit set when denormals are to be replaced by zero, the selector having a first input and an output, the first input comprising a floating point number, the selector selecting zero to become the output when the floating point number is denormal and the mode bit is set, the selector selecting the floating point number to become the output otherwise.