Abstract: A data and signaling time slot transfer and processing system for a set of multiplex lines comprises a switching matrix. Its inputs are connected to n multiplex lines by switching matrix input lines. There are m serial communication controllers each connected to an input register and an output register. The outputs of the switching matrix are connected by m output lines to the input registers. Its inputs are connected by m input lines to the output registers. The matrix outputs are also connected by n switching matrix output lines to multiplex lines. A composite clock signal is applied to all the input and output registers. A further clock signal is applied to the controllers, for the purpose of changing the information reception and transmission bit rates, the information having a bit rate of 64 kbit/s and the multiplex lines functioning at 2.048 Mbit/s.