Abstract: A synchronous memory (20) has parallel data output registers (34) and a dummy path (46). The output data from a memory array (22) is provided to the parallel output registers (34). The output registers (34) provide two parallel, interleaved, output data paths. The data in each path changes every other cycle of a clock signal. Dummy path (46) contains delay elements that model a propagation delay for a data path of the memory (20) during a read cycle. Using parallel data output registers (34) increases a time in which data is valid during the read cycle. The dummy path (46) tracks the output data signal in terms of process, power supply and temperature variations to ensure that the correct data is acquired during the read cycle.

Abstract: A CMOS dynamic RAM is described which uses multiplexing to selectively couple two pairs of bit lines to a single sense amplifier. Both pairs of bit lines are decoupled from the sense amplifier after a word line selects a cell and before sensing occurs in the sense amplifier. Only one pair of bit lines is coupled to the input/output lines of the memory. No dummy cells are employed. The bit lines are charged to one-half the power supply potential. Restoration of potentials on each pair of bit lines occurs at different times, thereby reducing the peak currents to the RAM.

Abstract: A method for testing an MOS, dynamic random-access memory employing full capacitance dummy cells is described. During probe testing a potential higher than the reference potential is applied to the dummy cells when reading binary zeroes from the memory and a potential lower than the reference potential is applied to the dummy cells when reading binary zeroes from the memory. This testing procedure detects weak cells and amplifiers and helps present the packaging of defective parts. In addition, a simplified means for programming redundant elements is described which requires substantially less substrate area than previous methods.

Abstract: An MOS dynamic RAM organized in a byte-wide arrangement is described. An internal bus is used for multiplexed column address signals and data. Other multiplexing reduced the lines associated with the input/output circuits. A unique power-on circuit automatically resets clock generators if they are not operative after power is applied.

Abstract: A signal generating circuit is provided which provides an output signal in response to an input signal. The output signal has minimum delay with respect to the input signal. The signal generating circuit has an inverter to receive the input signal. A cross coupled latch is coupled to the inverter and provides the output signal. A DC load stage is used as a load for the cross coupled latch. A transistor is coupled to the output signal to pull the output signal low upon command. Control circuitry is coupled to the transistor and helps precondition the signal generating circuitry so that it can respond to the input signal with minimum delay.

Abstract: There is provided a dynamic output buffer useful for providing output data from a memory. The output buffer includes a cross coupled sense amplifier having inputs and outputs. The outputs of this sense amplifier are coupled by output transistors to the output of the dynamic output buffer. The outputs of the cross coupled sense amplifier are also coupled to dynamic load devices which are used to prevent the outputs from deteriorating when the inputs are shunted or clamped to ground. The inputs are clamped to ground by transistors which are controlled by timing signals and thereby insure that data stored by the cross coupled sense amplifier will not be lost.

Abstract: There is provided a write circuit which is held in a disabled state until data is available to be written into the memory. This circuit is particularly useful for memories having one data in buffer and more than one memory block wherein each memory block has a write circuit to couple data in from the data in buffer. The write circuit has an input transfer device which is maintained in a disabled condition by an address signal until it is addressed. The output of the transfer device is maintained in a discharged state by the complement of the column address strobe. The output of the transfer device is coupled by a latch circuit to bit sense common lines in the memory.

Abstract: There is provided a dynamic output buffer useful for providing output data from a memory. The output buffer includes a cross coupled sense amplifier having inputs and outputs. The outputs of this sense amplifier are coupled by output transistors to the output of the dynamic output buffer. The outputs of the cross coupled sense amplifier are also coupled to dynamic load devices which are used to prevent the outputs from deteriorating when the inputs are shunted or clamped to ground. The inputs are clamped to ground by transistors which are controlled by timing signals and thereby insure that data stored by the cross coupled sense amplifier will not be lost.

Abstract: There is provided a dynamic output buffer useful for providing output data from a memory. The output buffer includes a cross coupled sense amplifier having inputs and outputs. The outputs of this sense amplifier are coupled by output transistors to the output of the dynamic output buffer. The outputs of the cross coupled sense amplifier are also coupled to dynamic load devices which are used to prevent the outputs from deteriorating when the inputs are shunted or clamped to ground. The inputs are clamped to ground by transistors which are controlled by timing signals and thereby insure that data stored by the cross coupled sense amplifier will not be lost.