Abstract: A graphics display apparatus with a combined bit buffer and character graphics store includes a coded display buffer containing pointers to the store. The store is constituted by odd and even memories used to derive bit patterns for odd and even character cell columns on the display and is partitioned into a font area and a bit buffer area. In a first mode of operation, compatible with existing programmed symbol arrangements, pointers in the coded display buffer in conjunction with odd/even select signals and slice signals derive the bit patterns for each raster scan line of the display. In a second mode of operation, a graphic image to be displayed is stored as a bit map in the bit buffer area: the required bit pattern is derived using slice and odd/even select signals in conjunction with pointers stored in the coded display buffer.

Abstract: A data display apparatus employs a raster scan cathode ray tube (1), a character refresh buffer (2) and three character row buffers (5,6,15) to address a character generator (3) in conjunction with a slice counter (4) or offset slice counter (18) under control of an events control module (20). This enables data within a partition on the CRT to be scrolled smoothly (scan-line-by-scan-line) and characters of different height (requiring different numbers of scans) to be displayed on the same row of the CRT.

Abstract: A programmable timing circuit for a cathode ray tube includes a register stack (48) in which events to be timed are stored so that they are presented to comparators (45, 46 or 47) in the sequence in which they will occur. Each event is coded in terms of the position (character, line or row) on the screen at which it is to occur and flags stored with the values are decoded to identify the event being timed when a match is found between the presented value and the count in a character, line or row counter (40, 41 or 42) which is indicative of the current beam position on the screen. Values in the register stack can also control internal operations of the timing circuit, for example re-setting counters or re-addressing the stack.