Abstract: A method to manufacture Copper Indium Gallium di Selenide (Cu(In,Ga)Se2) thin film solar cell includes evaporating elemental Cu, In, Ga, and Se flux sources onto a heated substrate in a single vacuum system to form a non-intentionally doped Cu(In,Ga)Se2 p-type conductivity layer and exposing the p-type conductivity layer to a thermally evaporated flux of Beryllium (Be) atoms to convert a surface layer of the p-type conductivity layer to an n-type conductivity layer resulting in a buried Cu(In,Ga)Se2 p-n homojunction. Also, the source of Be atoms includes a circular rod of Be having a uniform cross-section that is resistively heated and having its temperature controlled by passing an electrical current through the rod.

Abstract: Disclosed is a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT process relies on the formation of an “H-shaped” dielectric (i.e., Si3N4/SiO2) mask conformally deposited on top of the emitter contact metallization that is used to remove excess base metal through lift-off by a wet chemical HF-based etch. This HBT process also uses a thin selective etch-stop layer buried within the emitter layer to prevent wet chemical over-etching to the base and improves HBT reliability by forming a non-conducting, depleted ledge above the extrinsic base layer. The geometry of the self-aligned emitter and base metal contacts in the HBT insures conformal coverage of dielectric encapsulation films, preferably Si3N4 and/or SiO2, for reliable HBT emitter p-n junction passivation.

Abstract: Disclosed is a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT process relies on the formation of an “H-shaped” dielectric (i.e., Si3N4/SiO2) mask conformally deposited on top of the emitter contact metallization that is used to remove excess base metal through lift-off by a wet chemical HF-based etch. This HBT process also uses a thin selective etch-stop layer buried within the emitter layer to prevent wet chemical over-etching to the base and improves HBT reliability by forming a non-conducting, depleted ledge above the extrinsic base layer. The geometry of the self-aligned emitter and base metal contacts in the HBT insures conformal coverage of dielectric encapsulation films, preferably Si3N4 and/or SiO2, for reliable HBT emitter p-n junction passivation.

Abstract: Disclosed is a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT process relies on the formation of an “H-shaped” dielectric (i.e., Si3N4/SiO2) mask conformally deposited on top of the emitter contact metalization that is used to remove excess base metal through lift-off by a wet chemical HF-based etch. This HBT process also uses a thin selective etch-stop layer buried within the emitter layer to prevent wet chemical over-etching to the base and improves HBT reliability by forming a non-conducting, depleted ledge above the extrinsic base layer. The geometry of the self-aligned emitter and base metal contacts in the HBT insures conformal coverage of dielectric encapsulation films, preferably Si3N4 and/or SiO2, for reliable HBT emitter p-n junction passivation.

Abstract: Disclosed is a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT process relies on the formation of an “H-shaped” dielectric (i.e., Si3N4/SiO2) mask conformally deposited on top of the emitter contact metalization that is used to remove excess base metal through lift-off by a wet chemical HF-based etch. This HBT process also uses a thin selective etch-stop layer buried within the emitter layer to prevent wet chemical over-etching to the base and improves HBT reliability by forming a non-conducting, depleted ledge above the extrinsic base layer. The geometry of the self-aligned emitter and base metal contacts in the HBT insures conformal coverage of dielectric encapsulation films, preferably Si3N4 and/or SiO2, for reliable HBT emitter p-n junction passivation.

Abstract: The disclosed improved GaAs majority carrier rectifying barrier diodes comprise a p.sup.+ region between semiconductor regions that comprise n-doped material. Exemplary structures are n.sup.+ -i-p.sup.+ -i-n.sup.+ and n.sup.+ -n-p.sup.+ -n-n.sup.+. The improvement comprises use of carbon as the p-dopant and results in readily manufacturable reliable devices.

Abstract: A novel method of making a semiconductor device that comprises p-type III-V semiconductor material is disclosed. The method comprises heating of a graphite body such that the body serves as a sublimation source of carbon atoms that are incorporated into the III-V semiconductor material. Exemplarily, the carbon doped material is the base of a GaAs-based HBT.

Abstract: Electromagnetic radiation such as, in particular, infrared radiation is detected opto-electronically by means of a superlattice structure forming quantum wells having a single bound state; in the interest of minimizing dark-current, relatively wide barriers are used between quantum wells. Resulting highly sensitive, high-speed detectors can be used in optical communications, for terrain mapping, and for infrared viewing. Furthermore, upon application of a variable electrical potential across the superlattice structure, radiation traversing such structure can be modulated.

Abstract: A scalable and relatively easily manufacturable heterojunction bipolar transistor (HBT) comprises a thin (exemplarily 5-25 nm) emitter layer that serves as an etch stop layer and that furthermore passivates the extrinsic base region. The portion of the emitter layer that overlies the extrinsic base region is essentially fully depleted at all bias voltages in the normal operating range of the transistor. Base contact is established through the emitter layer, exemplarily by means of a metallized region on the emitter layer. A novel technique for carbon doping is also disclosed. Use of the novel technique makes possible a further embodiment of the inventive HBT, wherein base contact is made by means of Be implantation into the emitter layer.

Abstract: A floating gate memory device comprises a channel for conducting carriers from source to drain, a semiconductor heterostructure forming a potential well (floating gate) for confining carriers sufficiently proximate the channel so as to at least partially deplete it, and a graded bandgap injector region between the control gate and the floating gate for controlling the injection of carriers into and out of the potential well. Also described is a three element memory cell, including the memory device and two FETs, which operates from a constant, non-switched supply voltage and two-level control voltages. Arrays of memory devices may also be used to detect light in a variety of applications such as imaging.

Abstract: 36 We have discovered the III-V semiconductor layers with previously unattainably high effective hole concentrations can be produced by molecular growth processes (e.g. MBE) if an amphoteric dopant such as Be is used and if, during the growth of the highly doped III-V layer, the substrate is maintained at a temperature T.sub.g that is substantially lower than customarily used. For instance, a InGaAs layer with effective hole concentration 1.0.times.10.sup.20 cm.sup.-3 was grown at T.sub.g =450.degree. C., and a GaAs layer with effective hole concentration of 1.0.times.10.sup.20 cm.sup.-3 was grown at T.sub.g of 475.degree. C. The heavily doped III-V layers can be of device grade and can usefully be part of electronic devices such as high speed bipolar transistors.

Abstract: A floating gate memory device comprises a channel for conducting carriers from source to drain, a semiconductor heterostructure forming a potential well (floating gate) for confining carriers sufficiently proximate the channel so as to at least partially deplete it, and a graded bandgap injector region between the control gate and the floating gate for controlling the injection of carriers into and out of the potential well. Also described is a three element memory cell, including the memory device and two FETs, which operates from a constant, non-switched supply voltage and two-level control voltages. Arrays of memory devices may also be used to detect light in a variety of applications such as imaging.

Abstract: A narrow-bandwidth, high-speed infrared radiation detector is based on tunneling of photo-excited electrons out of quantum wells. Infrared radiation incident on a superlattice of doped quantum wells gives rise to intersubband resonance radiation which excites electrons from the ground state into an excited state. A photocurrent results from excited electrons tunneling out of quantum wells. Conveniently, Group III-V materials can be used in device manufacture. Preferably, quantum well potential barriers are shaped so as to facilitate resonant tunneling of photocurrents as compared with dark current. Preferred device operation is at elevated bias voltage, giving rise to enhancement of photocurrent by a quantum-well-avalanche effect.

Abstract: A transistor is described which the base region comprises a submonolayer of essentially only dopant atoms. One embodiment is a GaAs/AlGaAs heterojunction bipolar transistor in which the base region comprises a submonolayer of Be atoms. The effective base transit time is negligible in these transistors.

Abstract: A heterojunction bipolar transistor having means for changing carrier transport properties is described.

Abstract: An electronic oscillator being operable to detect millimeter wave and infrared frequency output signals over the range of 1-1000 GHz consists of a semiconductor device having a structure comprised of a first planar doped barrier region separated from a second planar doped barrier region by a superlattice region. Upon the application of a uniform electric field, the first planar doped barrier region operates as a means for injecting electrons into the superlattice region which then traverse to the second planar doped barrier region which operates as means for receiving the electrons. During transit through the superlattice region, the electrons undergo an oscillatory motion thereby making possible the detection of signals whose frequency is a function of the applied voltage and the periodic spacing of the superlattice.

Abstract: A passive millimeter wave image guide power limiter comprising a length of ielectric transmission line or waveguide for millimeter wave frequencies located on a relatively thin conductive ground plane forming thereby an image guide and including a planar doped barrier diode structure formed in the dielectric transmission line with the planar doped barrier structure being integrally grown in a slot milled in the constituent material, i.e. gallium arsenide, of the waveguide transversely across the width dimension thereof so as to be oriented perpendicular to the flow of RF power being propagated along its length dimension. The planar doped barrier structure becomes conductive at a predetermined power level to reflect any further incident RF power back toward the power source.

Abstract: A single planar doped barrier diode is grown by the selective deposition of gallium arsenide using molecular beam epitaxy (MBE) in the center of a gallium arsenide dielectric waveguide member mounted on a ground plane. The waveguide member includes two portions which extend in opposite directions and terminating in respective metal to dielectric waveguide transition sections which are coupled to an RF input signal and local oscillator signal, respectively. The planar doped barrier diode operates as an intrinsic subharmonic mixer and accordingly the local oscillator signal has frequency of one half the input signal frequency. An IF output signal is coupled from the mixer diode to a microstrip transmission line formed on an insulating layer fabricated on the ground plane. Dielectric waveguide isolators are additionally included on the dielectric waveguide segments to mutually isolate the input signal and local oscillator signal.

Abstract: A transferred electron semiconductor device in the form of an oscillator, for example, is fabricated by a molecular beam epitaxy growth process wherein a plurality of semiconductor layers are sequentially grown on a planar substrate. A pair of ohmic contacts are formed on the outer surface of the substrate and the uppermost layer with the resulting structure including two distinct intermediate semiconductor regions, the first being a drift region adapted to exhibit a differential negative resistance due to the transferred electron effect, and the second being a planar doped barrier region for accelerating electrons into the upper valley and injecting them into the drift region. By the use of a planar doped barrier a more uniform electric field is obtained along with a controlled lower barrier height whereby the transfer of electrons to the upper conduction band satellite valley can be made to occur over much shorter times and distances thus extending the upper frequency range of operation.

Abstract: Disclosed is an epitaxial layer field effect transistor having a planar dd barrier gate formed on an n-type semiconductor planar channel region between drain and source terminals formed on the surface of the channel region. The semiconductor channel region is fabricated on a semiconductor substrate, preferably GaAs and being separated therefrom by one or more semiconductor planar buffer regions. The planar doped barrier gate comprises an n.sup.+ -.pi.-p.sup.+ -.pi. structure grown by molecular beam epitaxy over the n-type channel region. Application of an electrical potential to the gate modulates the channel charge depletion in the semiconductor channel region underlying the gate causing a variation in the channel conductance laterally between the source and drain terminals.