Abstract: A method and an apparatus for uniform electroless plating of layers onto exposed metallizations in integrated circuits such as bond pads. The apparatus provides means for holding a plurality of wafers, and rotating each wafer at constant speed and synchronous within the plurality. Immersed in a plating solution flowing in substantially laminar motion and at constant speed, the method creates periodic superposition of directions and speeds of the motion of the wafers and the motion of the plating solution. The invention creates periodically changing wafer portions where the directions and speeds are additive and where the directions and speeds are opposed and subtractive. Consequently, highly uniformly layers are electrolessly plated onto the exposed metallizations of bond pads. If the plated layers are bondable metals, the process transforms otherwise unbondable pad metallization into bondable pads.

Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least portion a portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.

Abstract: A method and an apparatus for uniform electroless plating of layers onto exposed metallizations in integrated circuits such as bond pads. The apparatus provides means for holding a plurality of wafers, and rotating each wafer at constant speed and synchronous within the plurality. Immersed in a plating solution flowing in substantially laminar motion and at constant speed, the method creates periodic superposition of directions and speeds of the motion of the wafers and the motion of the plating solution. The invention creates periodically changing wafer portions where the directions and speeds are additive and where the directions and speeds are opposed and subtractive. Consequently, highly uniformly layers are electrolessly plated onto the exposed metallizations of bond pads. If the plated layers are bondable metals, the process transforms otherwise unbondable pad metallization into bondable pads.

Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.

Abstract: A microelectronic mechanical structure (MEMS) comprising a semiconductor chip having an integrated circuit including a plurality of micromechanical components, and a plurality of conductive routing lines integral with the chip; the routing lines having contact terminals of oxide-free metal; and the terminals having a layer of barrier metal on the oxide-free metal and an outermost layer of noble metal, whereby damage-free testing of the circuit is possible using test probe needles.

Abstract: A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of first barrier metal, deposited on the non-oxidized copper surface, having a copper diffusion coefficient of less than 1×10E-23 cm2/s at 250° C. and a thickness from about 0.5 to 1.5 &mgr;m. It further comprises a layer of second barrier metal on the layer of first barrier metal, having a diffusion coefficient of the first barrier metal of less than 1×10E-14 cm2/s at 250° C. and a thickness of less than 1.5 &mgr;m. It finally comprises an outermost layer of bondable metal, onto which a metal wire is bonded for metallurgical connection.

Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least a portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.

Abstract: A method and an apparatus for uniform electroless plating of layers onto exposed metallizations in integrated circuits such as bond pads. The apparatus provides means for holding a plurality of wafers, and rotating each wafer at constant speed and synchronous within the plurality. Immersed in a plating solution flowing in substantially laminar motion and at constant speed, the method creates periodic superposition of directions and speeds of the motion of the wafers and the motion of the plating solution. The invention creates periodically changing wafer portions where the directions and speeds are additive and where the directions and speeds are opposed and subtractive. Consequently, highly uniformly layers are electrolessly plated onto the exposed metallizations of bond pads. If the plated layers are bondable metals, the process transforms otherwise unbondable pad metallization into bondable pads.

Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.

Abstract: A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of first barrier metal, deposited on the non-oxidized copper surface, having a copper diffusion coefficient of less than 1×10E-23 cm2/s at 250° C. and a thickness from about 0.5 to 1.5 &mgr;m. It further comprises a layer of second barrier metal on the layer of first barrier metal, having a diffusion coefficient of the first barrier metal of less than 1×10E-14 cm2/s at 250° C. and a thickness of less than 1.5 &mgr;m. It finally comprises an outermost layer of bondable metal, onto which a metal wire is bonded for metallurgical connection.

Abstract: This disclosure describes a plating fixture to hold a silicon wafer containing integrated circuits in a metal plating bath. The wafer is coated with photoresist to a thickness equal to the desired bump height and the desired bump locations patterened by standard photolithographic techniques. The wafer is then loaded in the fixture and the fixture placed in the plating bath so that the patterned side of the wafer is facing up and the plating anode is located directly above the wafer. Systems presently on the market have the wafer positioned with the patterned side facing down and the anode located below it, or the wafer faces sideways and the anodes are access from it. These present systems allow air to be entrapped in the pattern of the photoresist, lowering yield by under plating or uneven plating of the bumps on the wafer. This disclosure prevents such yield loss and also allows cleanups on the wafer after it is loaded in the fixture.

Abstract: A substrate for mounting a flip-chip on a metallized circuit on the upper surface of the substrate. The substrate is silicon carbide condensed on a graphite or silicon core. The upper surface of the silicon carbide has a layer of insulating material comprised of silicon oxide, silicon nitride, aluminum nitride, boron nitride, an organic insulator such as polyimide, and diamond. The insulator prevents inadvertent shorting of the integrated circuit. The insulating layer can be deposited on the silicon carbide by such processes as chemical vapor deposition, sputtering, spinning or roller coating.

Abstract: This disclosure describes a plating fixture to hold a silicon wafer containing integrated circuits in a metal plating bath. The wafer is coated with photoresist to a thickness equal to the desired bump height and the desired bump locations patterned by standard photolithographic techniques. The wafer is then loaded in the fixture and the fixture placed in the plating bath so that the patterned side of the wafer is facing up and the plating anode is located directly above the wafer. Systems presently on the market have the wafer positioned with the patterned side facing down and the anode located below it, or the wafer faces sideways and the anodes are access from it. These present systems allow air to be entrapped in the pattern of the photoresist, lowering yield by under plating or uneven plating of the bumps on the wafer. This disclosure prevents such yield loss and also allows cleanups on the wafer after it is loaded in the fixture.

Abstract: A method of plating bumps on metallization on the face of a wafer, including the steps of placing the wafer in a transportable fixture wherein cathode needles press against the face of the wafer to make electrical contact and to force the back side of the wafer against a sealing member to prevent the plating bath from contacting the back side. The fixture with the wafer therein is placed in a clean up or presoak bath and is then transported to a plating bath without an operator having to touch the wafer.

Abstract: A transportable bump plating fixture and method for holding a semiconductor wafer in a face up orientation in a plating bath while plating bumps on the metallized circuitry on the wafer face. The fixture includes an elastomer pad which contacts the back of the wafer and forms a seal which prevents the plating bath from coming into contact with the back of the wafer. The fixture also includes means for forming a cathodic electrical connection to the metallization on the face of the wafer, and further includes a plating anode disposed above the face of the wafer. The fixture is open to the flow of the plating bath over the face of the wafer and between the face of the wafer and the anode.

Abstract: A bonding apparatus for bonding lead wires to a semiconductor surface includes a supply spool that contains a supply of the bonding wire that is fed to a capillary that is made of a non-conductive material. An electric arc forms a ball on the tip of the arc and the ball is retracted into the capillary. The ball is heated and compressed onto the semiconductor substrate and is then stitched over to a second bonding point which in most applications is the interface pin of the semiconductor device. The capillary has a non-conductive end that prevents coating of the capillary tip with the molten metal that results from the arcing of the bonding wire.