Abstract: A method for mask-to-wafer correlation among multiple masking levels of a semiconductor manufacturing process. The method includes creating compact targets containing structure patterns suitable for pattern placement, critical dimension and overlay measurement at a set of common locations on two or more patterning layers, and creating at least two masks containing functional circuit structure patterns and the compact targets at locations between functional circuit structure patterns. The method then includes measuring the targets, determining overlay variation between the masks, exposing and creating with one mask a first lithographic processing layer on a wafer, and exposing and creating with another mask a second lithographic processing layer on the wafer, over the first layer.

Abstract: A method of determining stitching errors in multiple lithographically exposed fields on a semiconductor layer during a semiconductor manufacturing process is provided. The method may include receiving a predetermined design distance corresponding to a plurality of petals associated with the multiple lithographically exposed fields and identifying a blossom within a single field-of-view (FOV) of a metrology tool, where the blossom is formed by a non-overlapping abutment of corners corresponding to the multiple lithographically exposed fields. The blossom may include the plurality of petals associated with the multiple lithographically exposed fields. Petal position errors may then be calculated based on both a coordinate position for each of the plurality of petals within the blossom and the predetermined design distance, whereby the calculated petal position errors are indicative of stitching errors for the multiple lithographically exposed fields.

Abstract: A method of determining stitching errors in multiple lithographically exposed fields on a semiconductor layer during a semiconductor manufacturing process is provided. The method may include receiving a predetermined design distance corresponding to a plurality of petals associated with the multiple lithographically exposed fields and identifying a blossom within a single field-of-view (FOV) of a metrology tool, where the blossom is formed by a non-overlapping abutment of corners corresponding to the multiple lithographically exposed fields. The blossom may include the plurality of petals associated with the multiple lithographically exposed fields. Petal position errors may then be calculated based on both a coordinate position for each of the plurality of petals within the blossom and the predetermined design distance, whereby the calculated petal position errors are indicative of stitching errors for the multiple lithographically exposed fields.

Abstract: Techniques, systems, and methods are provided for optimizing pattern density fill patterns for integrated circuits. The method includes adjusting an area of a scribe line and a density of dummy fill shapes in the adjusted scribe line, while maintaining an area of the die, to achieve a pattern density associated with technology ground rules for a particular design of the die.

Abstract: Techniques, systems, and methods are provided for optimizing pattern density fill patterns for integrated circuits. The method includes adjusting an area of a scribe line and a density of dummy fill shapes in the adjusted scribe line, while maintaining an area of the die, to achieve a pattern density associated with technology ground rules for a particular design of the die.

Abstract: A method and apparatus includes an integrated circuit device, and at least one alignment mark on the integrated circuit device, the alignment mark comprises a first coded region, a second coded region adjacent the first coded region, and a third coded region adjacent the second coded region, the second coded region located between the first coded region and the third coded region, and markings on the first coded region and the third coded region being identical.

Abstract: A method and apparatus includes an integrated circuit device, and at least one alignment mark on the integrated circuit device, the alignment mark comprises a first coded region, a second coded region adjacent the first coded region, and a third coded region adjacent the second coded region, the second coded region located between the first coded region and the third coded region, and markings on the first coded region and the third coded region being identical.

Abstract: A method for mask-to-wafer correlation among multiple masking levels of a semiconductor manufacturing process. The method includes creating compact targets containing structure patterns suitable for pattern placement, critical dimension and overlay measurement at a set of common locations on two or more patterning layers, and creating at least two masks containing functional circuit structure patterns and the compact targets at locations between functional circuit structure patterns. The method then includes measuring the targets, determining overlay variation between the masks, exposing and creating with one mask a first lithographic processing layer on a wafer, and exposing and creating with another mask a second lithographic processing layer on the wafer, over the first layer.

Abstract: A method of repeatedly exposing a pattern across a wafer in a sequential stepping process is disclosed. The pattern that is exposed includes at least one alignment mark. Each time the exposing process is repeated, the current exposure overlaps a portion of the wafer where the pattern was previously exposed and thereby erases a previously exposed alignment mark by re-exposing an area of the wafer where the previously exposed alignment mark was located. After the exposing process is repeated across the wafer, alignment marks remain only in the last exposed areas of the wafer.

Abstract: A method of repeatedly exposing a pattern across a wafer in a sequential stepping process is disclosed. The pattern that is exposed includes at least one alignment mark. Each time the exposing process is repeated, the current exposure overlaps a portion of the wafer where the pattern was previously exposed and thereby erases a previously exposed alignment mark by re-exposing an area of the wafer where the previously exposed alignment mark was located. After the exposing process is repeated across the wafer, alignment marks remain only in the last exposed areas of the wafer.

Abstract: A method of adjusting exposure of an energy beam to a lithographic resist sensitive to the energy beam, which method comprises determining where in a pattern to be exposed the energy level will exceed a critical thermal level, and adjusting the pattern and kind of exposure of the resist where the critical level is exceeded. One technique is to adjust the level exposure of the resist to a lower level equal to or less than the critical level with repeated exposures of the pattern in areas where the critical level is exceeded. The energy level monitored can be a thermal level measured as a temperature of the resist. A second technique is to adjust the exposure level by modifying the pattern and duration of exposure of the resist to a longer duration providing exposures equal to or less than the critical level with the modified pattern of exposures of the pattern in areas where the critical level is exceeded.