Abstract: A fabric shell uses a hollow, cylindrical body of polyethylene, which is provided with internal spacers and a urethane foam filling, to support tire cord fabric which is wound about the shell. The outer body of the shell is provided with circumferential grooves that grip the fabric and prevent it from shifting.

Abstract: A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidized sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidized sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).

Abstract: A process for fabricating a CMOS compatible bipolar transistor is described. The transistor, which is of the polysilicon emitter type, is fabricated by forming a p-type layer in a well, providing a polysilicon emitter in contact with the layer, using the emitter as a mask to implant p.sup.+ -type base contact regions, and applying contacts to the device.

Abstract: A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidised sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidised sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).

Abstract: A bipolar transistor structure (1) which can be used in an integrated circuit where bipolar (1) and CMOS transistors (2,3) are formed simultaneously on one substrate. In integrated circuit form the material, for example polycrystalline silicon, used for the gates (11,21) of the CMOS transistors is also used for the emitters (29) of the bipolar transistors, the collectors of the bipolar devices are comprised by doped wells (5) in the substrate (4) and the base contacts of the bipolar devices are comprised by regions (27,27a) equivalent to source and drain regions (17,18) of the n-well MOS transistors and bridged by base implants (28). The conventional CMOS processing is modified by the addition of two masking steps and one implant (base implant).

Abstract: A method of manufacturing a bipolar transistor (1) with semi-self-aligned p.sup.+ base contacts (27,27a). A p-type base region (28) is formed in a surface region of an n-type region 5 comprising a collector. An element (29) of, for example, n.sup.+ doped polycrystalline silicon, and comprising an emitter, is formed on the surface in contact with the base region (28). The base contacts (27,27a) are formed by implantation and using the element (29) as a mask. An n.sup.+ collector contact (25) is made to the n-tpe region (5).

Abstract: A bipolar transistor structure (1) which can be used in an integrated circuit where bipolar (1) and CMOS transistors (2,3) are formed simultaneously on one substrate. In integrated circuit form the material, for example polycrystalline silicon, used for the gates (11,21) of the CMOS transistors is also used for the emitters (29) of the bipolar transistors, the collectors of the bipolar devices are comprised by doped wells (5) in the substrate (4) and the base contacts of the bipolar devices are comprised by regions (27,27a) equivalent to source and drain regions (17,18) of the n-well MOS transistors and bridged by base implants (28). The conventional CMOS processing is modified by the addition of two masking steps and one implant (base implant).

Abstract: In making bipolar transistors, an interfacial oxide layer (5) is formed over ther monocrystalline region (1), and polysilicon (6) is formed both thereon as an extrinsic emitter region. After doping the polysilicon a monocrystalline emitter region (4) is produced in the base region by diffusion from the extrinsic polysilicon emitter region. The oxide layer (5) acts as a diffusion barrier to ensure that excessive dopant does not reach the monocrystalline region.After the above operation, a thermal treatment is effected at a higher temperature, e.g. 1100.degree. C., for a few seconds, which breaks down the interfacial oxide layer referred to above. This temporary use of the interfacial oxide layer leads to better and more consistant transistor characteristics.

Abstract: A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidized sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidized sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).