Abstract: A circuit for detecting when a fault condition has occurred includes an input stage responsive to a logic signal supplied to an input of the circuit for providing an output logic signal at an output thereof. An output stage, including a pulldown circuit, responsive to the output logic signal of the input stage, for providing an output logic signal at an output of the circuit. A fault detection circuit coupled to the output of the input stage and to the output stage for forcing the output of the circuit to a predetermined logic state when the pulldown circuit of the output stage is defective.

Abstract: An open bond detection circuit is provided for verifying the continuity through a bonding wire connected between an external pin and a bonding pad of an integrated circuit by monitoring the potential developed across a metal conductor connected between the bonding pad and the power supply conductor. An output signal is provided having a first state upon detecting substantially zero potential difference across the metal conductor and a second state when detecting a non-zero potential difference across the metal conductor. The first state of the output signal with substantially zero potential difference reflects an open bond between the external pin and bonding pad, while the second state of the output signal with non-zero potential difference indicates the bonding wire is intact.

Abstract: An ECL logic gate includes an input stage, an output stage, and a multifunction current mirror circuit. The input stage includes a plurality of input transistors, a reference transistor, and an output which indicates the relative conductivities of said reference transistor as compared to one or more of the input transistors. This output is coupled to the output stage. A current mirror circuit having first and second current paths is provided in which the input stage is coupled in series with the first current path, and the output stage is coupled in series with the second current path.

Abstract: An onboard structure used to terminate standard ECL devices of non-gate array devices which save space on the multichip module by requiring only non-discrete components. These non-discrete components include a first transistor having its collector coupled to the emitter of a second transistor, and its based coupled to the collector of a third transistor. Different variations of the onboard structure permit the structure to be a 50 ohm output, a 25 ohm output, a 60 ohm output, a series terminated output or a current sourced input termination.

Abstract: A high band width logic gate including a basic current switch logic block and emitter-follower output transistors. A switchable active circuit current sink is connected between an internal voltage switching node associated with the current switch logic gate and the emitter terminal of the emitter-follower output transistor. The active current sink is switched between a relatively low conductive state to a relatively high nonsaturating conductive state in order to maintain substantially constant current flow through the emitter-follower output transistor during switching of the logic gate in order to significantly improve AC beta roll off characteristics.