Patents by Inventor Roger L Valentine

Roger L Valentine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240427600
    Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.
    Type: Application
    Filed: September 6, 2024
    Publication date: December 26, 2024
    Applicant: Intel Corporation
    Inventors: Robert C. VALENTINE, Jesus Corbal SAN ADRIAN, Roger Espasa SANS, Robert D. CAVIN, Bret L. TOLL, Santiago Galan DURAN, Jeffrey G. WIEDEMEIER, Sridhar SAMUDRALA, Milind Baburao GIRKAR, Edward Thomas GROCHOWSKI, Jonathan Cannon HALL, Dennis R. BRADFORD, Elmoustapha OULD-AHMED-VALL, James C ABEL, Mark CHARNEY, Seth ABRAHAM, Suleyman SAIR, Andrew Thomas FORSYTH, Lisa WU, Charles YOUNT
  • Patent number: 12086594
    Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.
    Type: Grant
    Filed: August 28, 2023
    Date of Patent: September 10, 2024
    Assignee: Intel Corporation
    Inventors: Robert C. Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert D. Cavin, Bret L. Toll, Santiago Galan Duran, Jeffrey G. Wiedemeier, Sridhar Samudrala, Milind Baburao Girkar, Edward Thomas Grochowski, Jonathan Cannon Hall, Dennis R. Bradford, Elmoustapha Ould-Ahmed-Vall, James C Abel, Mark Charney, Seth Abraham, Suleyman Sair, Andrew Thomas Forsyth, Lisa Wu, Charles Yount
  • Patent number: 7132919
    Abstract: An integrated contact is disposed on the end of a conical coil form. Fine magnet wire is soldered to the integrated contact and wound around the coil form to fabricate a high-frequency inductor for use in high-frequency chokes and other high-frequency devices. In one embodiment, the integrated contact is plated on the tip of a polyiron coil form and less than one turn of wire is wrapped around the plated portion of the polyiron coil form. The integrated contact has reduced contact area, reducing capacitive coupling and improving high-frequency electrical performance.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: November 7, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: Michael J. Neumann, Roger L Valentine, Fred H. Hoppe, Andrew C. Duckhorn
  • Patent number: 6822162
    Abstract: A contiguous gasket provides an electromagnetic and environmental seal between the base and lid of a microcircuit housing. The base has a flat surface that allows easy access of tools for assembling electronic components. Channels are cut into a corresponding flat portion of the lid to accommodate the electronic components mounted on the base. High-frequency feedthroughs are brought through sidewall connector features of the base that rise above the assembly surface. Feedthroughs are optionally brought through the flat portion of the base as well. When the microcircuit housing is assembled, the lid compresses the gasket against the base to form an electromagnetic and environmental seal.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: November 23, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Roger L. Valentine, Anthony R. Blume, Michael J. Neumann, Adam E. Robertson